Monthly Archives: September 2015

ASE purchase 5% of rival SPIL

Mergers and acquisitions happen very frequently in the semiconductor industry. However, what it is not common that these kind of operations proceed smoothly, quickly and without hurdles. This is the case of the public takeover of Siliconware Precision Industries (SPIL) for Advanced Semiconductor Engineering Inc (ASE). Indeed, the company dealing with the agreement (KGI) just confirmed a very small progress on the negotiation (less than 5%).


The reason behind the delayed progression of the process is to be found in SPIL’s negative attitude towards the acquisition.  As a matter of fact, SPIL ’s chairman, Lin Wenbo, recently released an open letter to its shareholders where he was highlighting a possible underestimate of the agreed selling price, together with a series of not favorable positions of the company towards the market if the acquisition would get to a positive conclusion. According to Wendbo, in fact, this last situation would particularly make the company lose important opportunities for the future; hence, his urge for the shareholders to review the acquisition deal.


ase spil


In addition to what already said, Wenbo, rightfully pointed out that, despite ASE statements of investing in SPIL only due to financial reasons, they also contemporary mentioned that this acquisition would be helpful to face the increasing competition on the market. In conclusion, what ASE affirms appear quite contradictory for a company interested only in financial investments. As Wenbo said: “The two statements were completely contradictory, showed that ASE is deliberately to take over SPIL.”

TSMC to Quit Solar Business Activity

We all know that solar energy will face a positive growth in the next future. However, Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) is moving countertrend by announcing its intent of quitting the solar energy subsidiary activity with TSMC.


Indeed, the big foundry is expecting to close the manufacturing operation by August 2015. The decision  arrived after selling, last January, also its LED-making subsidiary TSMC Solid State Lighting, to Epistar Corp. (Hsinchu, Taiwan) for about NT$825 million (about $25.8 million).



SOLAR PRICES PLUNGE Since the 1970s the cost of photovoltaic panels has decreased from nearly $80 a watt to an average of $.63, driving a solar boom worldwide.



The unexpected decision of quitting the solar energy market is due to a bad entrance timing in the industry and, above all, by an inefficient economy of scale that heavily impacted on the cost reduction’s ability.


Sure enough, TSMC Solar’s employees don’t have to worry about their future. The Big foundry already offered job offers to them together with assuring warranty covers to all its clients.



Graphic Source: Paul Maycock; BNEF


Financial Obstacles Delaying 450mm Wafers Development

According to the latest report released by IC Insights, Global Wafer Capacity 2015-2019 shows a delay in 450mm wafers’ development and production in contrast to an increased 300mm wafers’ consumption by technology companies.


Judging from statistics, in fact, despite the huge economic incentives that would be generated on the production scale by adopting the 450mm wafers (up to 20% in savings), companies are facing incredible hard times to cope with the huge financial and technology obstacles that are afflicting the development and transition to the larger wafer.



Reports say it clear: the progress of the 450mm wafers is growing at an incredibly slow pace which hasn’t shown any attempt of improvement during 2014. Insiders’ forecasts are not too bright either. Indeed, the most influential operators of the industry say that the adoption of these wafers will happen only by 2020; maybe, in the best scenarios, some early adopters will start the production a couple of years before in order to test the market.


Silicone wafers in a carrier


Another chart, always related to the mentioned report, shows the trend of IC fabs using the 300mm wafers. Before entering into the chart’s detail, it is worth to specify that this kind of products are used only inside high volume commodity type devices (like flash memories), image sensors, power management devices, complex logic and micro-component ICs with large die sizes and by foundries that can fill a 300mm fab by combining wafer orders from many sources. Getting back to the chart, it is shown that, after a short period decrease back in 2013, due to the closure of 3 large fabs, 300mm IC fabs were numbered 87 during 2014, expecting 23 more by the end of 2019. These number shows, once again, the evidence of a delayed entrance of 450mm wafers on the market.


GlobalFoundries rumored to be acquired by the Chinese

GlobalFoundries is probably doing something right because China has set its eyes on GlobalFoundries with rumors of a possible imminent acquisition. Indeed, thanks to several strategical decisions, GlobalFoundries is offering today a unique portfolio, both CMOS and SiGe processes, cutting-end technology (14nm and 22FDSOI) and a global semiconductor manufacturing footprint.



The decision of acquiring GlobalFoundries, came after the Chinese company received the denial for the acquisition of Micron, and subsequent to ATIC  (Abu Dhabi’s Advanced Technology Investment) rumored release of its holdings in GlobalFoundries.




Hua Capital Management, renowned for being the resourceful firm capable of successfully close the acquisition of Omnivision (the smartphone camera sensor manufacturer), has approached GlobalFoundries in order to persuade the firm to be acquired. however, there is one relatively big problem standing on the path: Samsung license agreement with GlobalFoundries for the 14nm FinFET process.


Indeed, Samsung will firmly stand against the Chinese investment and will oppose to it in order to avoid any possible future competition. Time will tell how things will evolve and get to an end.




Low Parasitic HBM ESD Testing

The Human Body Model (HBM) Electrostatic Discharge (ESD) test is the oldest and most widely used ESD test in the electronics industry. The JEDEC HBM test isn’t static; it has been revised to keep up with the rapid changes in the semiconductor industry. The latest revision of the spec addresses failures that are caused by parasitic impedances in HBM testers. EAG has the equipment and expertise to help you solve your HBM test problems.


Evolution of the HBM Spec


The current ANSI/ESDA/JEDEC HBM test, JS-001-2014, evolved from the military ESD testing spec, MIL-STD-883, Method 3017.8. The first JEDEC version of the spec was published in 1995. Over the last twenty years, incremental improvements have been made to the HBM spec based on the data and analysis performed by reliability engineers from a cross-section of the IC industry. One of the main goals has been the reduction of the cost and time required for HBM testing. Other changes have addressed issues with the HBM simulator hardware. The following table summarizes the different revisions of the HBM spec:


hbm testing table


Idealized Model of the HBM Tester


An idealized model of an HBM tester is shown in Figure 1.

idealized HBM tester

Figure 1 – Idealized HBM Tester


In this model, a 100pF capacitor is charged with a high voltage power supply, not shown in the diagram. The supply is removed from the circuit, and the capacitor is discharged through a 1500Ω resistor. In this case, the device under test is the simplest one possible: a piece of wire. If you measure the current through the piece of wire as a function of time, the waveform looks like the one shown in Figure 2.

HBM current vs time

Figure 2 – HBM Current vs. Time, +1000V HBM


A More Realistic Model of the HBM Tester


The waveform in Figure 2 shows some ringing, suggesting that there are parasitic impedances in the circuit. Parasitic impedances are any combination of extra unwanted passive devices (resistors, capacitors and inductors) in the signal path. For the discharge of an HBM simulator through a piece of wire, a more realistic circuit is shown in Figure 3.

more realistic HBM tester model

Figure 3 – A More Realistic HBM Tester Model


Because relays are used to connect the terminals of the device under test (DUT) to the HBM tester, parasitic inductance and resistance is added to the discharge path. In real HBM simulators, the 1500Ω resistor is distributed, with approximately 1400Ω on the Terminal A side and 100Ω on the Terminal B side. The resistance is divided in order to provide an in-spec waveform across the entire relay array.



Because most IC devices have more than two terminals, the situation is more complicated. Every pin on the device has a capacitively-coupled impedance path to the HBM simulator, whether the pin is connected or not. When one pin of a multi-pin power or ground group is stressed, the other pins in that group are floated, and they add additional capacitance, on the order of 4-8pF per pin. This extra capacitance can significantly change the shape of the waveform. In addition, the DUT board and socket also add additional resistance, inductance, and capacitance, causing additional changes to the HBM waveform. Any circuitry that is sensitive to the waveform slope or to the Terminal B resistance can be affected by parasitic impedances. It is even possible to damage non-stressed pins during HBM testing because of capacitive coupling. All of these can impact the waveform and cause false HBM failures (See Reference 6.) An even more realistic model of the HBM tester is shown in Figure 4.

an even more realistic HBM tester model

Figure 4 – An Even More Realistic HBM Tester Model


A Reduced Parasitic HBM Tester


To address the problems that have been seen with relay-based systems, the last three versions of the ESDA/JEDEC HBM test allow the use of a low parasitic HBM tester. The interface between the tester and the DUT is a probe station; the part is electrically connected at two points only. No special fixtures or sockets are required, and there is no relay array resulting in reduced parasitic impedance. The DUT can be a packaged part or a wafer. Critical structures can be characterized earlier in the design cycle. (See Figure 5.)


HBM two point teser and probe station

Figure 5 – HBM Two Point Tester and Probe Station


The low parasitic tester provides a highly accurate and nearly perfect HBM pulse. Voltage vs time and Current vs. Time can be measured while the pulse is being applied to the DUT. This allows a more thorough analysis of the DUT’s behavior during the HBM stress. (See Figure 6.)


Two point HBM tester waveform and I-V curve
Figure 6 – Two Point HBM Tester Waveform and I-V Curve


EAG’s Two Point Tester Approach


Because a two point tester is still too slow to do tests on large production parts, EAG has adopted a hybrid test strategy, using the available relay testers.

  1. Test the DUT on a relay tester. This is allowed by the spec, and it’s the highest speed and lowest cost solution.
  2. Minimize tester parasitic impedances by using the following practices:
    a. When a multi-pin supply or ground plane is Terminal B (grounded terminal), tie all of the pins to ground.
    b. When a multi-pin supply, ground, or non-supply group is Terminal A (zapped terminal), don’t zap all pins; zap a representative pin instead.
    c. In the supply/ground to supply/ground tests, zap positive polarity only.
  3. If there are no failures at ATE, the DUT has passed the test.
  4. If failures are observed or if characterization data is required:
    a. Do further stressing to identify and isolate the failing pin pairs.
    b. If a pin pair passes on the two-point tester, the device passes.
    c. If a pin pair fails, use the two-point tester to characterize the failure.




With the rapid changes in process technology, false failures due to relay tester parasitic impedances has become a more important HBM issue. EAG’s testing approach minimizes the incidence of false failures. EAG has the capability to determine if you have a false failure using a two-point tester. This leads to fewer mask changes and faster time to market for EAG customers. You can count on EAG to provide you with the latest standards and best testing practices available in the industry.




  1. JEDEC JESD22-A114, “Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM),” (Other revisions were A, B, C, D, E.)
  2. ANSI/ESDA/JEDEC JS-001-2014, “Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM),” (Other revisions were 2010, 2011, 2012.)
  3. E.Grund, M. Hernandez, Oryx Instruments, “Methods to Remove Anomalies from Human Body Model Pulse Generators,” EOS/ESDA Symposium 2006
  4. Evan Grund, Grund Technical Solutions LLC, “Two-Pin Human Body Model Testing,” EOS/ESDA Symposium 2009
  5. Scott Ward, Keith Burgess, Joe Schichl, Charvaka Duvvury, Peter Koeppen, Hans Kunz, Texas Instruments; Evan Grund, Grund Technical Solutions, “Overcoming the Unselected Pin Relay Capacitance HBM Tester Artifact with Two Pin HBM Testing,” EOS/ESDA Symposium 2010
  6. Yue Zu, Liang Wang, Rajkumar Sankaralingam, Scott Ward, Joe Schichl, Texas Instruments; “Threshold Voltage Shift due to Incidental Pulse on Nonstressed Pins during HBM Testing,” EOS/ESDA Symposium 2014



This is a guest post by EAG which provides early engineering services. Read more here.


AnySilicon Surpasses ChipEstimate in Website Ranking

AnySilicon, the semiconductor vendors marketplace and IP portal reveals today its official website ranking measured by the global leader in website analytics.


In the past ChipEstimate and Design-Reuse were the only players in the IP portal market. But in Jan-2015 AnySilicon has launched a new IP portal in addition to its already semiconductor vendors marketplace.


According to measurements performed by in September-2015, AnySilicon has improved its traffic and it is ranked 778,100 worldwide (the lower the better), with 4.2 daily pageviews per visitor spending 3:46 minute per visit.


Alexa Inc. is a California-based subsidiary company of Amazon that is known for its toolbar and website. Alexa provides traffic data, global rankings and other information on thousands of websites.





AnySilicon vs. ChipEstimate Ranking Comparison


The following charts show the increase in AnySilicon’s traffic (and thus the decrease in ranking position) in the last 6 months. The chart also shows the crossing point in July-2015 when AnySilicon traffic exceed ChipEstimate.

 AnySilicon Platform Offering