Monthly Archives: November 2015

Understanding MultiCore Designs

Over many years and based upon Moore’s Law, transistor counts have doubled approximately every 24 months as features increase and semiconductor dies grow. This has led to performance increases of 1000x over 20 years with microarchitecture advances and faster transistors.



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With the technology, developers obtained performance increases through processor upgrades, clock frequency boosts and microarchitecture improvements. However, processor designs ran into power and performance limits of single core processors, focus shifted to multicore designs.


There are three basic classes of multicore architectures: homogeneous multicore (with same ISA) with shared memory (PCs & Servers); heterogeneous multicore (different ISA) with mix of shared and non-shared memory; and homogeneous multicore (same ISA) with non-shared memory.


With the shift to multicore, responsibility for performance gains has moved into software and away from technology scaling. New supporting software libraries, development tools and technologies allow skilled software engineers to continue to improve performance.


Many companies are adopting an incremental approach to enable multicore processors based on their business needs.




While the PC market is slowing, the focus has shifted to embedded multicore processors in mobile, automotive and communication markets with some of the cores implemented as accelerators for various algorithms.


Hardware trends have led to scalable on-chip multiprocessors, lots of inter-processor communication, fast responsive programmable input- output channels and various mixed signal blocks. A variety of algorithms and techniques requiring predictable execution (flat memory hierarchy; predictable caches) and multithreading with low synchronization overhead.


Additionally, a low-power/energy-efficient multicore market has evolved to support the “Internet of Things,” including wearables with support for computing in clouds.


Some of applications require high instantaneous performance (vision, automotive requires embedded intelligence). They need to be real- time, secure, highly reliable and energy/power efficient, available in a small form factor and easy to use. For the large consumer market where lower cost is fundamental, we must rethink the architecture and build SOCs like memories with many repeated regular blocks with behavior defined by software.


For improved energy efficiency, asynchronous techniques are being used at block levels. However, overall SOC performance may be limited by data movement more than by processing engines requiring scalable and predictable on chip interconnect.


On Chip Interconnect


Until the 1980s, computing has been expensive and communication cheap but with continuous technology scaling this has changed. Thehigh-density of the components in the SoC complicate the design and implementation of a shared bus architecture. In today’s System-on- Chip (SoC) that include as many as 300 -500 different IP blocks, fast communication between different IPs is implemented using a well- structured design approach called Network-on-Chip (NoC).


A design methodology is needed in order to make efficient use of all on chip the resources, with programming models and predictable behavior. The basic performance parameters of NoC are latency, bandwidth and jitter. The basic cost factors are power consumption and area usage.


Designing energy efficient methodologies for various NoC domains, such as the routing algorithms, buffered and buffer-lessrouter architectures, fault tolerance, switching techniques, voltage islands, and voltage-frequency scaling significantly affects the NoC performance. Therefore, the optimization of routing algorithms for the NoC is a key concern in enhancing the NoC performance and in order to minimize the energy consumption.


EDA Tools and Trends


For the embedded consumer market where lower cost is key volume driver, we will need various innovations occurring in multiple areas such as process technology, chip architectures and software, and the need for improvement in SOC implementation is a must.


EDA innovations are key part of the equation. We need:


  • Improvement in design productivity (design cycle reduction for design, verification, layout and silicon validation), to support multi-billion transistor designs.
  • Reduction in power consumption (fast on/off mixed signal designs, leakage power verification etc)
  • Seamless hardware/software co-design (block modeling, virtual prototyping, compiler performance validation etc)
  • System level integration


To see improvement in areas listed above requires improvement in EDA tools and methodology.




This is a guest post by Hem Hingarh, VP, Synapse Design

Verification IP : Changing landscape

For decades, EDA industry has been working out options to improve their offerings and ensure silicon success for the semiconductor industry. A few decades back, while the EDA giants were unknown, design automation was exercised individually in every organization developing a product. Gradually these tools moved out of the design houses and the ‘make vs buy’ decision carved a new league with EDA front runners. Talking specifically about verification, while the simulation tools were procured from outside, the in house CAD groups were still required to develop a flow for automation, self checking, regression management and data analysis. In the last decade, all of this came up as a package from EDA vendors thereby further squeezing the CAD teams in the design houses. So, what next?  Well, the recent acquisitions in this space i.e. Cadence acquiring DenaliSynopsys acquiring nSys and ExpertIO indicate where we are heading. Initially the VIP providers were able to sustain with licensing and basic verification support model but now the pressure is surmounting as VIPs get commoditized. The VIP only vendors will have to identify themselves either with the EDA vendors or with Design service providers wherein the VIPs complement other offerings. Before moving ahead let’s discuss what is a VIP?


What is a VIP?

A Verification IP is a standalone ‘plug and play’ verification component that enables the verification engineer in verifying the relevant DUT (design under test) module at block, sub system and SoC level. Based on the need, the VIP can act as a BFM to drive DUT signals or MONITOR the signals and VALIDATE them for correctness and data integrity. It may have a set of protocol CHECKERS and test scenarios to confirm compliance with the standards (if any) or COVER groups identifying corner cases and test completeness. VIPs are developed using HDLs or HVLs with standard methodology or as a set of assertions. It needs to have enough APIs providing flexibility for modifying the internal units as per DUT. User should be able to extend the available monitors, scoreboard and checker hooks while developing a verification environment around this VIP. Ease of developing scenarios at different levels using available functions and sequences is important in minimizing the verification turn around cycle. Quick integration with other tools like coverage, simulate, debug and transaction analysis is critical in successfully deploying the VIP.  Finally the most crucial is the support provided by the VIP vendor to the user in responding to issues and upgrading the VIP as the standards evolve.


The common VIPs available include –


– MIPI protocols like DSI, CSI, HSI, SlimBus, Unipro, DigRF & RFFE.

– Bus protocols like AXI, AHB, APB, OCP & AMBA4.

– Interfaces like PCIexpress, USB2.0, USB3.0, Interlaken, RapidIO, JTAG, CAN, I2C, I2S, UART & SPI.

– Memory models & protocol checkers for SD/SDIO, SATA, SAS, ATAPI, DDR2/DDR3, LPDDR etc.

Companies providing the above VIPs fall into one of the below categories –


– EDA vendors

– VIP only providers (some of them offering IPs also)

– Design services companies


Although, there is a lot of IP development still continuing with the design houses, the motivation to procure VIP from outside is much higher for obvious reasons.


While the increasing demand of VIPs would drive more participants to enter this space, there are significant challenges to come up with a decent VIP portfolio.


Challenges for new entrants


– Which protocol(s)/standard(s)? SoC design houses are well aware of their requirements, but any other entity wanting to invest in developing the VIPs to license further needs to engage with potential customer(s) and build the team with right skill set accordingly.


– Which HVL and Methodology? Starting with an early customer helps in resolving this. However the risk is that the other potential customers may want a different HVL & Methodology. The current trends indicate that development with SV (IEEE 1800) and UVM is a safe bet.


– Expertise with domain/protocol and VIP development? Building a team without a design partner would mean bringing in domain experts along with VIP developers. Further the team needs to be around after implementation so as to work with customers for VIP deployment, fix bugs, modify based on customer requirement and upgrade as the standards evolve.


– How to validate the VIP? Initial clean up may involve short circuiting the Master & Slave agents of the VIP. To prove it golden, either it has to be validated with an already available golden VIP in the market (added cost) or working with a strategic customer who is willing to try out this solution on the already available golden IP or IP under development. Note that it takes significant cycles for the VIP to mature.


– Inter operability with tools? Once the VIP is working with one set of tools, it is important to evaluate it with other simulators. Porting of the VIPs to work on the emulators and formal tools (if applicable) should be planned next. Note that all tool vendors have alliance programs to facilitate such requirements.


– Additional cost? Apart from engineering & tool cost, membership to the standard bodies contributes to additional cost. Members are required to pay yearly fees for adopting the standard to develop a commercial product.


If new comers have a challenge to enter this arena, what should the existing partners of this ecosystem do?


SoC Integrators


When the focus is on rolling out SoCs, investing into in-house development of a VIP for standard protocol(s) doesn’t help in adding any differentiation to the end product. VIP development would incur cost towards tool licenses and engineers during and after development as resources would be required to support multiple projects deploying the VIP, fix bugs and upgrade the VIP as standards evolve at a fast pace. For big design houses getting a good deal with vendors would clearly direct ‘buy’ decision. For startups, utilizing resources to get the product out faster is more important than investing into VIP development. Getting into strategic engagement with VIP providers is a better solution.



EDA Vendors


Investing into VIP makes perfect sense for the EDA vendors for multiple reasons.

– The cost of development reduces with the tool sets available in house.

– The licensing model for the VIP is same as that of tools and complements the product portfolio quite well.

– The sales channel can be reused since the customer base is same.

– If the solution has limited competition it can open up sockets with new customers while making sure that the design houses sticking to vendor specific flow are maintained.

– The VIP(s) can be used as a test vehicle for validating the tools.

– With cloud computing picking up, a strong VIP portfolio will help in offering cloud based verification services quite easily.


Design Service Providers


For design service providers, it is good to invest in VIP development as it complements the services offered. Since they work with both SoC integrators and EDA vendors it makes sense for them to get into partnerships with either or both of these parties instead of developing a solution standalone. Sub system as an IP shall pick up soon. This is where the design services companies should invest by building a complete verification environment and test suite to verify these sub systems while partnering with the IP & VIP providers.


Changing landscape ….


Verification has been the forte for India. Whether to get the right skill set or reduce cost, the verification engineers from India have been involved at all levels i.e. VIP development, IP verification or SoC verification. Geographically, the changing landscape on the VIPs point the efforts to be converging from SoC integrators, EDA vendors and Design service providers in India.





This a guest post by Gaurav Jalan, general chair at DVCON India

China to invest $47B to build world leading chip company

The Chinese investment company, Tsinghua Unigroup Ltd, plans to invest $ 47 billion in the next five years to become the world largest chipmaker.


In an interview, Chairman Zhao Weiguo hinted Reuters that the next few weeks there could be a purchase deal for a big chip maker in the United States. “If you can’t be the top-three giant, it will be very hard to develop your business in the chip industry,” he told Reuters.


The name of Tsinghua increased recently highlighted by two key events: In September 2014 it signed a cooperation agreement with Intel, which Intel has invested $ 1.5 billion for 20% stake. The strategic agreement with Intel includes implementation of joint research and development, marketing and joint future investments.


In July this year tried Tsinghua to purchase the memory manufacturer Micron for $ 23 billion. But this attempt was not successful.

Which companies will invest to support Flip Chip growth?

Due to the growth of the semiconductor business, the wider adoption of Cu pillar solutions and the introduction of Flip Chip technology for LED and CMOS Image Sensors (CIS) applications, the Flip Chip market is expending. Under this context, more and more industrial companies including OSATs, IDMs IC foundries and bumping house undertake in this market.
The “More than Moore” market research and strategy consulting company Yole Développement (Yole) explored this industry and proposes today a detailed technology and market report, entitled “Flip Chip: Technologies & Market Trends”. Yole’s team is daily discussing with the leaders of the Advanced Packaging industry. Based on these interactions, the consulting company highlights the evolution of the technical needs and market trends. These major results make Yole’s analysts to think that full capacity should be reached in 2017.
What are the required investments to support this growth? Are there competitive technologies such as TSMC’s new solution, high-performance integrated fan-out wafer level packaging (InFO-WLP), that could answer the market needs and compete Flip Chip technology?…
Under “Flip Chip: Technologies & Market Trends” report, Yole’s advanced packaging team provides an overview of Flip Chip technology and market trends. The company reviews the competitive landscape including player dynamics and key market trends; they also detail the Flip Chip market capacity and wafer forecast. Yole’s report also includes a detailed technology roadmap.



“Based on the discussions we had with the major advanced packaging companies, at Yole, we think that demand for Flip Chip is expected to reach the current maximum capacity in 2017“,
 says Santosh Kumar, Senior, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. And he adds: “Therefore, new investment will be needed starting in 2018.”

Since Cu pillar processing can be performed by standard foundries and IDMs, the supply chain may see some slight modification. Yole’s analysts expect higher investment in Cu pillar 12” line wafer bumping lines from wafer foundries such as TSMC and SMIC. This change will affect OSATs’ wafer bumping revenue since foundries will gain market share.
OSATs will maintain their strong position in wafer bumping and assembly thanks to of their huge experience and low cost solutions. Their business model enables them to better control the supply chain, as they provide for the complete set of flip-chip services: package design and qualification, wafer bumping, substrate in-sourcing, assembly and final test.


However, big IDM companies like Intel and Samsung maintain their dominance in terms of wafer bumping capacity. “At Yole, we expect that even in 2020 Intel will remain the highest-capacity player in Cu pillar wafer bumping”, comments Thibault Buisson, Technology & Analyst, Advanced Packaging at Yole. Foundries and OSATs are also establishing joint ventures for wafer bumping to provide turnkey solutions to customers from chip fabrication to assembly at competitive cost.
And what about the Chinese companies? Do they have a role to play in the Flip Chip market? Chinese players are significantly increasing their presence in wafer bumping and Flip Chip assembly by mergers and acquisitions. JCET acquired STATS ChipPAC and FCI was acquired by Tianshui Huatian Technology Company.


This is a guest post by Yole Développement

Top 10 semiconductor Companies – 2015

IC Insights will release its November Update to the 2015 McClean Report later this month, and its new 2016 edition of The McClean Report in January.  The November Update will include the latest IC market forecasts by product type through 2019, a detailed forecast for semiconductor industry capital spending by company for 2016, and a ranking of the top-25 semiconductor suppliers’ forecast for 2015 (the forecasted top-20 2015 semiconductor suppliers are covered in this research bulletin).


Since all of IC Insights’ figures are presented in U.S. dollars, a strengthening U.S. currency deflates foreign sales and market results while a weakening U.S. dollar serves to inflate the sales and market figures.  Thus, the rare occurrence of significant strengthening of the U.S. dollar versus the four major currencies shown in Figure 1 is expected to deflate the combined 2015 semiconductor sales growth rate of the top 20 suppliers by four percentage points.  Moreover, the strong U.S. dollar is forecast to lower the total worldwide semiconductor market growth rate by three percentage points to -1% this year.


Figure 1


This currency “deflation” effect presents itself in the form of lower semiconductor average selling prices (ASPs), which are forecast to register a 3% decline this year.  The continuing strength of the U.S. dollar throughout 2015 is one of the reasons IC Insights lowered its IC market forecast for this year from +1% to its current -1% expectation.


The forecasted top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 2015 is depicted in Figure 2.  As shown, it is expected to take just over $4.4 billion in sales just to make it into the 2015 top-20 ranking and seven of the top-20 companies are forecast to have 2015 sales of at least $12.0 billion. The ranking includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore.  The top-20 supplier list includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and five fabless companies.  If the three pure-play foundries were excluded from the ranking, Japan-based Sharp would be ranked 18th, U.S.-based AMD 19th, and China-based fabless supplier HiSilicon 20th.


Figure 2


IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are clearly identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.


Not all foundry sales should be excluded when creating marketshare data.  For example, although Samsung is expected to have a large amount of foundry sales in 2015, some of its foundry sales were to Apple and other electronic system suppliers.  Since the electronic system suppliers do not resell these devices, counting these foundry sales as Samsung IC sales does not introduce double counting.  Overall, the top-20 list in Figure 2 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.


Some highlights of the forecasted top-20 semiconductor supplier ranking for 2015 are shown below.


•    In total, the top-20 semiconductor companies’ sales are forecast to be flat in 2015, one point higher than the growth rate expected for the total worldwide semiconductor industry.


•    Using the 2014 exchange rates per U.S. dollar, the combined top-20 semiconductor suppliers are forecast to show a 4% increase (note: the semiconductor sales figures for Avago, ST, and NXP were not adjusted since they report their sales in U.S. dollars).


•    Although the top-20 semiconductor companies are forecast register 0% growth in 2015, there is expected to be a 52-point spread between Avago, the fastest growing company on the list (23%), and Renesas, the worst performing supplier (-22% in U.S. dollars, -11% in yen) in the ranking.


•    In 2014, Intel’s semiconductor sales were 36% greater than Samsung’s.  In 2015, the delta is forecast to drop by a whopping 15 percentage points to only 21%.  Moreover, Samsung’s “currency adjusted” semiconductor sales for 2015 are forecast to be only 11% less than Intel’s.


•    One new entrant is forecast to break into the top-20 ranking in 2015—Taiwan-based pure-play foundry UMC, which is expected to replace U.S.-based AMD.  AMD is forecast to have a particularly rough 2015 with its sales expected drop 28% this year to about $4.0 billion.


•    Infineon is forecast to register the highest “currency adjusted” 2015 semiconductor industry growth at 39%.  Even if International Rectifier’s (Infineon’s purchase of IR was completed in January of this year) estimated $1.1 billion in 2015 sales were excluded from Infineon’s results this year, the company would still be forecast to show a 20% increase in sales expressed in euros.


•    One of the real “star performers” on the list is Sony.  As shown, even with the tremendous weakness of the yen versus U.S. dollar, the company is forecast to register an 11% increase in semiconductor sales when expressed in U.S. dollars and a 27% surge in sales in its local currency, the Japanese yen.  Sony is having tremendous success in sales of image sensors and is expected to more than triple its semiconductor capital spending this year to put in additional capacity for image sensor production.


•    The pending mergers of Avago and Broadcom and NXP and Freescale will have a significant impact on future top-20 rankings.  The combination of Avago and Broadcom’s sales in 2015 ($15.4 billion) is forecast to be enough to move the company into the 6th spot while the combined 2015 sales of NXP and Freescale ($10.2 billion) are forecast to be enough to move the new entity into the 8th position.  IC Insights believes that additional acquisitions and mergers over the next few years are likely to continue to shake up the future top-20 semiconductor company rankings.


This is a guest post by IC Insights

Google Will Design a Mobile Phone CPU

Google is taking the next necessary steps towards the mobile phone market and plans to start developing and producing CPU chips for enabling a complete mobile phone eco system, to be combined with its successful Android operating systems.



Google has started in recent weeks talks with several processors manufacturers, to be involved in the early stages of planning the processor and maybe other peripheral components.


According to a report published in The Information met Google officials in recent days with representatives of a number of producers and processors, and presented them with a long list of ingredients, they want a plan in full cooperation.


According to sources familiar with the matter, Google wants first and foremost to design the CPU itself, ie, core smartphone processors, as among other things Google wants to increase the cache (Cache) containing processors.


Other components are components faster camera and built-in support depth cameras, such as the company’s Tango Project. By dictating the technical specifications of the processors, Google will ensure that Android phones will run smoothly, with no “bottlenecks” and all the new features it plans to combine its future operating systems, work well.