Monthly Archives: December 2015

The 4th C in Verification

The 3C’s of verification i.e. Constraints, Checkers & Coverage have been playing an important role enabling faster verification closure. With growing complexity and shrinking market windows it is important to introduce the 4th C that can be a game changer in actually differentiating your product development life cycle. Interestingly the 4th C is less technical but highly effective in results. It is agnostic to the tool or flow or methodology but if introduced and practiced diligently would surely result in multi-fold returns. Since verification claims almost 70%of the ASIC design cycle, it is evident that timely sign off on DV would be the key to faster time to market of the product. Yes, the 4th C I am referring to is Collaboration!


UVM demonstrates a perfect example of collaboration within the verification fraternity to converge on a methodology that benefits everyone. Verification today spreads beyond RTL simulations to high level model validation, virtual platform based design validation, analog model validation, static checks, timing simulations, FPGA prototyping/emulation and post silicon validation. What this means is that we need to step out and collaborate with different stakeholders enabling faster closure.


The first & foremost being the architecture team, RTL designers & analog designers who conceive the design and realize it in some or the other form and many a times fall short of accurate documentation. The architecture team can help to a large extent in defining the context under which theverification needs to be carried out thereby narrowing down the scope. With a variety of tools available, the DV teams can work closely with designers to clean the RTL removing obvious issues that otherwise would stall simulation progress. Further, assertion synthesis and coverage closure would help in closing the verification at different levels smoothly. Working with analog designers can help tune the models and their validation process wrt the circuit representation of the design. This enables faster closure of designs that see increased scope of analog on silicon.


Next are the tools that we use. It is important to collaborate with the EDA vendors in not just being the user of the tool but working closely with them in anticipating the challenges expected in the next design and be early adopters of the tools to flush the flows and get ready for the real drill. Similarly, joining hands with the IP & VIP vendors is equally crucial. Setting up right expectations with the IP vendors on the deliverables from verification view point i.e. coverage metrics, test plans, integration guide, integration tests etc. would help in faster closure on SoC verification. Working with VIP vendors to define how best to leverage the VIP components, sequences, tests & coverage etc. at block and SoC level avoids redundant efforts and help in closing verification faster.


The design service providers augment the existing teams bringing the required elasticity to the project needs or take up ownership of derivatives and execute them. These engineers are exposed to a variety of flows and methodologies while contributing to different projects. They can help in introducing efficiency to the existing ways of accomplishing tasks. Auditing existing flows and porting the legacy environment to better ones is another way these groups can contribute effectively if partnered aptly.


Finally the software teams that bring life to the HW we verify. In my last blog I highlighted the need for HW & SW teams to work more closely and how verification teams acts as a bridge between the two. Working closely with the SW teams can improve reusability and eliminate redundancies in the efforts.



Collaboration today is the need of the hour! We need to be open to recognize the efforts put in by different stakeholders from the ecosystem to realize a product. Collaboration improves reuse and avoids a lot of wasted efforts in terms of repeated work or incorrect understanding of intent. Above all, the camaraderie developed as part of this process would ensure that any or all these folks are available at any time to jump in the hour of need to cover for unforeseen effects of Murphy’s law.






This a guest post by Gaurav Jalan, general chair at DVCON India

Freescale to Improve Semiconductor Manufacturing Utilization

Optimal+, a leader in Manufacturing Intelligence solutions, today announced that it was selected by Freescale® Semiconductor to deliver their enterprise software suite to enhance the efficiency of their global manufacturing operations. In a move intended to improve the utilization of Freescale’s manufacturing equipment worldwide, the two companies signed a multi-year agreement under which they will collaborate to also improve processes at Freescale’s internal and external manufacturing facilities.





Optimal+ delivers the industry’s first proven enterprise solution that builds manufacturing intelligence that measurably improves semiconductor product yield, throughput and quality through early detection. The company’s solutions enable a paradigm shift in the manufacturing data infrastructure of semiconductor companies to provide rapid, actionable intelligence that can be used to optimize every measurable link in their global supply chain.


“Our global market leadership position in microcontrollers and digital networking processors depends rests on our ability to continually monitor our supply chain for speed, efficiency and cost,” said Brian Belden, vice president of final manufacturing operations at Freescale Semiconductor. “With Optimal+ we are positively impacting our culture to become more proactive in our manufacturing operations and are improving how we leverage the big data generated across our global manufacturing operations to achieve significant improvements in equipment utilization, test time and product yield.”


From test and yield engineers to managers and C-level executives, data generated throughout the manufacturing process is an invaluable source of information to ensure quality, prevent unnecessary waste and maximize capital equipment efficiency. Optimal+ delivers this information in a global, unified view and with unprecedented speed to address the manufacturing challenges faced by the semiconductor industry.


“We are delighted that Freescale has chosen Optimal+ and we look forward to helping them maximize the efficiency of their global manufacturing supply chain,” said Dan Glotter, founder and CEO of Optimal+. “We are committed to empowering our customers to manufacture intelligence from every aspect of their manufacturing processes and enable them to generate measurable value from that information.




IDMs Could Top Fabless Semiconductor Company Growth

IC Insights will release its new 2016 McClean Report late next month.  The 2016 McClean Report will include a ranking of the top-50 semiconductor suppliers’ for 2015 as well as the top-50 fabless semiconductor suppliers.  The forecasted “post-merger” top-10 2015 IDM and fabless semiconductor suppliers are covered in this research bulletin.


Unlike the relatively close annual market growth relationship between fabless semiconductor suppliers and foundries, fabless semiconductor company sales growth versus IDM (integrated device manufacturers) semiconductor supplier growth has typically been very different (Figure 1).  In 2010, for the first and only time on record thus far, IDM semiconductor sales growth (35%) outpaced fabless semiconductor company sales growth (29%).  Since very few fabless semiconductor suppliers participate in the memory market, the fabless suppliers did not receive much of a boost from the surging DRAM and NAND flash memory markets in 2010, which grew 75% and 44%, respectively.


As shown in Figure 2, only three of the top-10 IDM semiconductor suppliers are forecast to register growth in 2015 and, in total, the top-10 IDMs are expected to display flat growth this year.  Although flat growth by the top-10 IDMs would typically be considered poor performance, it is still forecast to be a much better result than is expected from the top-10 fabless semiconductor suppliers (Figure 3).  In order to make direct comparisons for year-over-year growth, IC Insights combined the merged, or soon to be merged, companies’ 2014 and 2015 semiconductor sales regardless of when the merger occurred.


As shown, the top-10 fabless semiconductor suppliers are forecast to register a 5% decline in sales this year, five points worse than the top-10 IDMs.  It should be noted that essentially all of the decline expected for the top-10 fabless suppliers in 2015 could be attributed to the forecasted decline in Qualcomm/CSR’s sales this year.  Much of the sharp decline in Qualcomm/CSR’s sales this year is being driven by Samsung’s increasing use of its internally developed Exynos application processor in its smartphones instead of the application processors it had previously sourced from Qualcomm.


Figure 1

Figure 2

Figure 3

Application processor sales to fabless/system house Apple from pure-play foundry TSMC are included in the fabless company sales ranking under the “Apple/TSMC” moniker.  Application processor sales supplied to Apple from IDM-foundry Samsung are included as part of Samsung’s logic IC sales.


As mentioned in the title of this Research Bulletin, 2015 could end up being only the second year ever, after 2010, in which the IDM semiconductor suppliers outpace the fabless semiconductor suppliers with regard to year-over-year growth.  Whether this actually takes place will be revealed from IC Insights’ extended compilation of the IDM and fabless semiconductor company rankings for the 2016 McClean Report.

Report Details:  The 2016 McClean Report



This is a guest post by IC Insights

AnySilicon Hotline ™ offers free answers to semiconductor questions

[Press Release]  AnySilicon, the fastest-growing semiconductor marketplace has announced today the availability of a free semiconductor hotline service offering expert-level answers to technical and commercial ASIC questions. Using this free service companies can better meet schedule and budget objectives and avoid wrong decisions due to lack of information.


The hotline service builds on the expertise of multiple ASIC professionals that provide objective answers to technical inquiries and cost-related questions. Some examples include finding IP cores, identifying ASIC design partners, understanding tapeout and wafer costs, selecting the best fit technology, understanding package trade-offs and cost issues, conducting feasibly studies and more.


The new service expands AnySilicon’s platform, which includes a semiconductor marketplace, IP Potral, Semipedia (Semiconductor Wikipedia), forums and technical articles to help ASIC engineers and managers make smarter decisions.


The hotline service has already been used with over 100 inquiries, answered free of charge with a 24-hour average response time.


To try the new AnySilicon Hotline please click here.