Monthly Archives: January 2016

FPGA vs ASIC, What to Choose?

This is a high level article for those who are debating whether to use FPGAs or ASICs and need some technical and commercial insight to help ease the decision process. Both technologies, ASICs and FPGAs are absolutely fantastic and have great benefits but it’s up to you to figure out, based on your product which technology to use. In some cases there is a clear advantage to FPGAs and in other cases ASICs are in advantage.


In this article you find the main differences and comparisons in between the two technologies: FPGA vs ASIC. If you are still unsure about which path to choose, please contact our staff here.




FPGAs (Field Programmable Gate Arrays) are chips created originally in 1985 to perform only digital functions but today they have already both analog and mixed signal blocks. Customers like to use FPGA because they are easy to use, and cost effective reprogrammable devices.  FPGA are known for their flexibility and their ability to be reprogrammed in the field. There is no need to have a full blown design flow and tooling, therefore the NRE investment is very low and as consequence time to market is fast.


The problem is that FPGAs are not fully customable, for example, one cannot add a specific analog block or integrate RF capability into an FPGA, those functionalities need to be implemented by external ICs, thus making the product larger in size and more costly.




ASICs (Application Specific Integrated Circuits) are specific chips (as the name suggest) used to implement both analog and digital functionalities in high volume or high performance. ASICs are full custom therefore they require higher development costs in order to design and implement (NRE). Moreover, unlike the FPGAs chips, they are not reprogrammable and therefore a change requires again NRE payment.


On the other side, however, ASICS are much denser, and one can integrate several different functionalities into one chip and therefore offer small size, low power and low cost solution.


FPGA vs ASIC small

(get here a higher resolution image)


FPGA vs ASIC Frequently Asked Questions




I need a chip with flexibility to accommodate future updates, should I use an FPGA?




If you mean future hardware changes (compared to software updates), then an FPGA would be the best solution because an FPGA can be updated with new hardware functionality. ASIC’s hardware is constant and not suited for future updates. Today, there are ASIC IP cores that offer FPGA functionality that can be embedded into the ASIC, allowing parts of the ASIC to be programmable.




My initial budget is low, and I expect low volume production, should I use an FPGA?




Absolutely. FPGA does not require costly EDA tools or any production tooling (such as maskset). If your production volume is low, then FPGA would be an ideal solution. ASIC will start showing a financial benefit in mid-size and high volume production runs and has higher upfront cost and steep learning curve.




My design is power sensitive, which technology to choose, ASIC or FPGA?




It’s most likely that ASIC would be the best solution in case you need to design your circuit to use less power. FPGA does not provide a lot of room for power optimization, while a custom-made ASIC can be definitely designed to consume very low power. In addition to that, there are power management method used in ASIC to allow further power optimization such as power gating and clock gating.




My design needs to run at extremely high speed, would ASIC be the best solution?




Yes, an optimized design running on an ASIC would run faster than a general-purpose FPGA.




Our design has at least 50% analog circuitry, which technology would be the best match?




If the analog circuitry does not exist as part of the FPGA offering (such as SERDES or ADC blocks) then the only choice you have is to go for the ASIC path. An ASIC can accommodate both Analog and Digital blocks easily.



Price Comparison FPGA vs ASIC


Let’s take an example that shows the total cost of ASIC and FPGA technology including both NRE and production unit price.



ASIC Unit Cost: $4



FPGA Unit Cost: $8





The graph clearly shows that after volume of 400K units, ASICs are starting to be more cost effective. Therefore, despite the fact that the ASIC project requires $1.5M in NRE, after 400K unit the ASIC is starting to return the investment, compared to an FPGA.




In conclusion, both ASIC and FPGA are technologies with different benefits, however their difference relies on costs, NRE, performance and flexibility. In general, we can say that for lower volumes’ designs, FPGA flexibility allows to save costs and obtain better results; while ASICs chips are more efficient and cost effective on high volume applications.


Next Steps – ASIC


If you are looking for an ASIC design company you may want to start your journey on this page.


Next Steps – FPGA


However, if you are seeking an FPGA design company try this website.


Verification IP : Build or Buy?

Consumerism of electronic products is driving the SoC companies to tape out multiple variants of products every year. Demand for faster, low power, more functionality and interoperability is forcing the industry to come up with standard solutions for different interfaces on the SoC. In past couple of years, tens of new protocols have shown up on silicon and equal no. of protocols has been revised spreading their description to thousands of pages. Reusability is the key to conquer this level of complexity both for design and verification. The licensing models for IPs & VIPs vary and many design houses still are in the dilemma on ‘Make vs Buy’ for verification.


Why BUILD Verification IP?


Points that run in favour of developing in-house VIP solutions include –


– Cost of licensing the VIP that front loads the overall design cost for a given project.

– Availability of VIP for a given HVL, methodology & simulator.

– Encrypted VIP code aggravates the debug cycle delaying already aggressive schedules.

– VIP & simulator from different vendors lead to further delay in root causing issues.

– Verification environment developed with a VIP ties you to a vendor.

– DUT specific customizations need to be developed around the VIP. Absence of adequate configurability in available solutions poses a high risk to verification.


Why BUY Verification IP?


While obvious, reasons why to procure the VIP include –


– Reusability advocates focusing on features that differentiate the final product and leave the innovation on standard solutions to relevant experts.

– Developing a VIP comes with a cost. A team needs to be identified, built and maintained all throughout with a risk that attrition would lead to risk at critical times.

– Time to market is important. Developing/upgrading in house VIP may delay the product itself.

– For new protocols or upgrades to existing ones, there would be a ramp up associated with protocol knowledge and this increases the risk with internally developed solutions.

– Probability of finding a bug and the end product being interoperable is high with third party solutions that have experienced different designs.

– Architecting a VIP is easier said than done. Absence of an architecture & process leads to multiple issues.

– In house solutions may not be reusable across product lines (different applications) or projects due to missing configurability at all levels.  Remember verification is all about JUGAAD and such philosophy doesn’t work with VIP development.

– With increasing adoption of hardware acceleration/emulation for SoC verification, there is need to develop transactors to reuse VIP leading to additional effort which otherwise would be done by vendor.

– Poorly developed VIP can affect the simulator/accelerator performance badly in general and at SoC level in particular. This in turn would affect the productivity of the team. To be competitive, vendors would focus on this aspect which is otherwise missing with internal solutions.

– External solutions come with example cases and ready to use env giving a jumpstart to verification. For in-house solutions the verification team may end up experimenting to bring up the environment adding to delays.


Clearly the points in favour of BUY outweigh the BUILD ones. Infact the ecosystem around VIP is evolving where solutions are available to the issues favouring MAKE too. With standard HVLs and methodologies like UVM, simulator agnostic VIP is relatively easy to find. Multiple VIP vendors and design service providers with a VIP architecture platform are getting into co-development of VIPs to solve the problem of specific language, methodology, encryption and availability of transactors for acceleration. Customization of VIPs to address DUT specific features or enable transition from one vendor solution to another is also on the rise through such engagements.


With this, the debate within the organization needs to move from BUILD vs BUY to defining the selection criteria for COLLABORATION with vendors who can deliver the required solution with quality at desired time.



This a guest post by Gaurav Jalan, general chair at DVCON India

MPWs: Catalyst of IC Production Innovation

Necessity is the mother of invention. For the semiconductor industry, the emergence of Multi-Project Wafers (MPWs) is no exception to the rule. This fundamental enabler of affordable IC fabrication emerged in the 1970’s to help university researchers and silicon entrepreneurs prototype their Integrated Circuits (ICs) and demonstrate their work. It was the early days of the semiconductor industry when firms like IBM, Intel, Fairchild, and others were applying tremendous innovation toward building smaller, faster and cheaper chips.


The standard chip design textbook at the time was the groundbreaking “Introduction to VLSI Systems,” a collaborative work by computer science pioneers Lynn Conway and Carver Mead. Conway was a visiting professor at MIT. Mead was at Caltech. The book and early courses taught by both professors marked the beginning of the Mead & Conway revolution in VLSI system design.


By 1983, the book was being used at more than 100 universities — training new generations of chip designers, sparking new IC design tools and methodologies, and laying the foundation for today’s electronic design automation industry.


Their contributions to the semiconductor industry extended far beyond creating a formal IC design curriculum. They also pioneered a new internet-based model for rapid-prototyping and short-run fabrication of chip designs in large quantities. Known as Multi-Project Wafers (MPWs) or Multi-Project Chips (MPCs), the model combined designs from multiple companies or diverse designs from a single company and integrated them onto one wafer for production. Mask and wafer costs were shared and sample lots of up to 1,000 devices could be created at costs as low as 10 percent of a dedicated wafer run. It was a revolutionary concept at the time and helped build critical mass for silicon innovations.





MOSIS: The MPW Pioneer


The first well-known MPW service was MOSIS which was established by DARPA in 1981.


At first, MPWs simply provided a channel for researchers and silicon entrepreneurs to prototype their IC designs. Its relevance and value soon became apparent to commercial firms who viewed MPWs as a practical prototyping vehicle that allowed designers to debug and perform essential design adjustments before making substantial strategic investments.


MOSIS was quick to respond. To meet growing demand for MPW services — from domestic and international customers — the organization began to build alliances with a global network of foundry partners. At the same time, in-house expertise was boosted to create a competent, expert interface between IC designers and their fabrication partners. Designs were pooled into common lots and run through the fabrication process at partner foundries. The completed chips (packaged and/or unpackaged) were returned to customers.


Over time, most advanced silicon fabrication facilities began to offer MPW services. However, MOSIS has remained at the center of the effort. Since inception, the organization has fabricated more than 60,000 IC designs for a broad mix of customers. They include commercial firms, government agencies, and research and educational institutions. While they initially used MPWs to prototype, many are now turning to MPWs to volume produce their IC designs. They’re drawn by the model’s flexibility and affordability. For example, to optimize profitability, some companies use a larger portion of the real estate for production chips and a smaller portion to produce prototypes of next-generation chips.


Driving new Cycles of MPW Innovation through Automation


Today, the legacy of MPW innovation is more evident at MOSIS than ever. Only now, the stakes are much higher. Turning a design into silicon has never been more challenging. Process technologies are highly advanced. The manufacturing ecosystem is complex and production costs are soaring.


For fabless IC entrepreneurs, the cost barriers are formidable. It’s not easy for them to access the leading-edge technology required to fabricate their devices. At large companies where R&D budgets are constrained and margins tight, cost is also a challenge. For design teams working on new-generation products beyond the company’s mainstream portfolio, an affordable prototyping- to- volume-production solutions model is more appealing than ever. It saves money, reduces risk, and speeds time to market.


MOSIS has kept pace by continually streamlining its service offerings, stripping much of the red tape that often comes with the fabrication process, and increasing the value of the MPW model. Automation is central to the effort.


By making its website the control center, the MOSIS service is optimized for simplicity and ease of use. This is essential for designers facing ultra-tight market windows. From this hub, designers can access the information they need quickly and efficiently, and proceed promptly.


The process is straightforward. First, customers are invited to open a MOSIS account. Then, they’re asked to select a process from a comprehensive list. To enhance transparency and facilitate budgeting, detailed pricing and schedule is offered. From there, the process technology files can be promptly downloaded, and design and verification essentials can be performed. Once that’s done, the GDSII files can be seamlessly submitted to MOSIS via secure FTP. A design review is then performed before committing the files to the customer’s preferred fab partner for processing. Following that, it’s off to test and assembly. Once that’s complete, the packaged die is returned to the customer by MOSIS.


At all times, customers have a secure window on the process — with visibility at each step enabled by a sophisticated tracking dashboard.


Over the years, MOSIS has found that its customers — commercial and academic — are singularly focused on fabricating their designs with minimum fanfare. So the organization continually boosts its MPW services with features to improve automation. For those who are new to the process, in-house expertise is available to advise and guide them, bringing the benefits of MOSIS’ three-plus decades of MPW expertise, knowledge, and experience to their production needs.




This is a guest post by MOSIS


Need help with MPW?




Top Semiconductor Foundries Capacity 2015-2016 (Infographic)

On a yearly basis, AnySilicon provides a snapshot of top semiconductor foundries wafer capacity, based on available data on their website. In our last yearly report , we have presented semiconductor foundries capacity ranking of the top 4 pure-play wafer fabs: TSMC, GLOBALFOUNDRIES, UMC and SMIC. This year, our report has been expanded to include top 10 wafer foundries consisting of both pure-play and non-pure-play foundries. The results are interesting because we have managed to include Samsung’s fab capacity as well.


Each of the top semiconductor foundries holds several production sites that address different technology nodes and wafer sizes. Naturally, the goal of each company is to sell 100% of the production capacity (sometimes even more) to reach revenue goals.


Why is wafer capacity important? Capacity means potential sales. For example, if GloFo will sell its entire yearly wafer capacity it will still not be able to reach to TSMC’s revenues. Simply because TSMC has more wafer capacity to sell. Thus if GloFo is planning to be #1 player in the semiconductor market they need to double their wafer production capacity.


semiconductor foundry capacity 2015


Intel is by far the largest semiconductor player in the market but they don’t have more capacity than GloFo. The reason that Intel generates more revenue than GloFo is because Intel has a different product:  they sell complete chips rather than wafers. They sell solutions to a market that can accept higher margins. When companies sell solution their gross margin per product is higher, therefore Intel is able to generate more sales even they have smaller wafer capacity.


 Click here to download the Semiconductor Foundry Capacity Ranking (9MB). 



The 2 Easiest Ways to Find IP Cores

IP cores availability and quality have become a critical factor to any SoC design success. Engineers have to find and qualify different IP cores quickly and effectively to help boost time to market and reduce the need of unnecessary re-spins.  Moreover, with today’s aggressive time to market demands and the ever increasing cost of maskset – companies will buy more IP cores and hence spend more time of finding, evaluating and managing IP cores instead of developing IP cores internally.


According to the market research done by Semico Group the average number IP cores required for a typical SoC design in 2016 is 175(!). This means that in average 175 IP cores are integrated in a typical SoC design in 2016 and this number is set to increase to 200 IP cores in 2018.


By acknowledging this fact and considering the amount of time that needs to spend on finding IP cores, AnySilicon is offering 2 easy ways to find IP cores,  AnySilicon is here to help with finding IP cores by 2 simple ways:


Option 1: Send your IP list to AnySilicon (estimated time: 2 min)


Step 1: Go to “Get 3 Quotes from” menu and select “IP Vendors”


Get 3 quotes


Step 2: Fill in the form with your IP cores requirements. AnySilicon staff will do the research for you (anonymously if you choose “hide my email”) and will get back to you with results within a short period.


get 3 quotes1


Option 2: Search AnySilicon IP Core Directory  (estimated time: 10 min)


Step 1: Use the search tool on AnySilicon site using specific keywords such as PLL.


search IPs


Step 2: The search tool will show you relevant results of different IP core vendors, this will allow you to browse the list and then go directly to each vendor’s profile page to learn more about the IP core availability.


PLL search


Amazon is starting to sell SoCs

The semiconductor industry was a bit puzzled last year when Amazon acquired Annapurna Labs (Israel) for $350 million; the analysts believed that Amazon is planning to use Annapurna’s chips in its own data centers. But now it turns out that Amazon is taking advantage of the deal to enter the market and compete head-on with chipmakers.
Annapurna operates as a subsidiary of Amazon, under the name Annapurna Labs. Last week Amazon announced it was starting to sell the chip developed at Annapurna, named Alpine. This is a complete system-on-chip, based on the 32-bit ARMv7 architecture with an additional 64-bit ARMv8 with. It serves as a processor for communications routers, storage systems (Network Attached Storage), home automation systems, accessories, IoT and more.

Today’s home routers are limited because of the shortage of processing power, thus limiting the added value services that vendors can provide. In addition, it forces many customers to purchase additional devices to improve the level of connectivity, storage, media management in the home devices, the Internet and other media.
The company explained that this is because routers are home based on simple processor (CPU) and external hardware accelerators need very deep software optimization in order for them to meet the performance required by market.
Alpine chip tackles this problem by providing an array of resources that includes a quad-core CPU processing, storage network interfaces, PCIe Gen3 and 10Gbps Ethernet. In addition, it includes telecom-level subsystems, such as DDR4 memory and L2 cache of 2MB.
The new chip supports both Linux and FreeBSD. The open source community has been developing a large number of applications, such as video streaming, security, cloud connectivity and more.


The announcement came after the chip has been incorporated into various designs such as: Wi-Fi routers, NAS products and gateways.