Monthly Archives: January 2017

AnySilicon Offers Instant Price Quotes From ASIC Vendors

AnySilicon, the fast-growing semiconductor marketplace has announced today the availability of a new service allowing decision makers to receive instant price proposals from ASIC Design Companies, Semiconductor Foundries, Assembly and Test companies, and IP Core Vendors.

 

 

AnySilicon new service allows companies to easily receive price quotes and evaluate different vendors’ proposal in time range of 24-48 hours. ASIC vendors bidding on specific project are located around the world with specific domain expertise and various business models. Using this free service companies can better meet schedule and budget objectives and avoid wrong decisions due to lack of information.

 

The AnySilicon marketplace is an ecosystem comprising of the entire spectrum of semiconductor services (IC design, verification,  assembly, wafer supply, test, qualification and failure analysis suppliers) of world’s leading semiconductor services companies and vendors offering IP cores.

 

The new platform allows users to improve silicon time to market, quality and budget by selecting a set of suppliers that perfectly match any silicon project requirements.  The additional IP vendor directory will help users access a complete SoC ecosystem covering IP vendors, IC design houses and manufacturing services.

 

The new service expands AnySilicon’s platform, which includes a Semiconductor Services marketplace, IP Portal, Forum, Semiconductor Wikipedia, and technical articles to help ASIC engineers and managers make smarter decisions.

 

Link to the new service.

 

 

Media contact: Press@anysilicon.com

 

news

Sonics Collaborates with GLOBALFOUNDRIES to Accelerate Adoption of Power and Performance Capabilities of the 22FDX® Process by SoC Designers

San Jose, Calif. – January 25, 2017Sonics, Inc., the world’s foremost supplier of on-chip network (NoC) and power management technologies and services, today announced it will collaborate with GLOBALFOUNDRIES on energy processing unit (EPU) product development that leverages the power and performance optimization capabilities of the 22FDX® process technologies for the system-on-chip (SoC) design community. The collaboration seeks to raise the level of abstraction for SoC power control through the integration of 22FDX body-biasing techniques into Sonics’ comprehensive EPU products. Sonics will develop an extension of its EPU product line, based on the ICE-Grain™ Power Architecture, which supports GLOBALFOUNDRIES body-biasing library components to increase SoC performance, reduce SoC power consumption, and enable SoC designers to tightly tune margins for higher manufacturing yields. As part of the collaboration with GLOBALFOUNDRIES, Sonics has also joined the FDXcelerator™ Partner Program.

 

“Sonics is on a mission to bring power management to every SoC design team and our collaboration with GLOBALFOUNDRIES is an important element in that strategy,” said Grant Pierce, CEO of Sonics. “We want to make SoC designers more comfortable adopting aggressive power management techniques to control energy consumption. FDX™ technologies offer amazing abilities to trade off transistor speed versus leakage power to optimize power grains to varying workloads. Our EPU will provide a safe and automated solution that removes the perceived risk of using these sophisticated power management techniques while enabling different regions of the chip design to dynamically operate at different biases.”

 

“GLOBALFOUNDRIES is building a world-class ecosystem to enable customers to leverage 22FDX and collaborating with Sonics is key to simplifying customer adoption of body-biasing in their designs,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES. “Our customers need a scalable method for controlling the unique body-biasing capabilities offered in the 22FDX process, and applying FDX to Sonics’ pioneering work in EPU will bring power saving results to designers with power sensitive SoCs.”

 

22FDX: Architected for Effective Body-biasing

One of the most differentiated features of the 22FDX platform is that it is architected for effective body-biasing. Body-biasing applies a positive or a negative voltage to the back gate of the transistor. This allows the transistor threshold voltage (Vt) to be tuned, either higher or lower, and can be done statically or dynamically under software or hardware EPU control. In the case of reverse body-bias, the Vt is increased to reduce the leakage in standby mode operation. For appropriately optimized device architectures, leakages down to 1pA/micron are achievable.

 

In the case of forward body-bias, the switching frequency can be increased and used for a selectable boost or turbo mode to increase performance. Forward body-biasing can also be used to enable ultra-low power or low voltage operation, even down to 0.4 volts, by lowering the Vt to retain voltage headroom and performance while operating at low Vdd. There are many other novel ways to use body-biasing, such as process compensation to minimize variability or as a method to mitigate the reliability penalties associated with voltage overdrive conditions.

 

Dynamic Body-bias Provides Best Performance – Power Tradeoffs

When body-biasing corners are combined with traditional PVT corners, designers have access to an entirely new dimension to optimize for power and performance. With the body-bias capability of 22FDX, they can optimize circuit blocks to maximize battery life with the ideal combination of active or leakage power based on the desired use condition. The figure below shows the optimal operating points for relative active and leakage power to obtain best performance, lowest total power or best performance per watt. This flexibility enables innovative solutions to the difficult trade-offs designers face when using other process technologies.

 

Figure
Source: GLOBALFOUNDRIES’ 22FDX whitepaper March 2016

 

About GLOBALFOUNDRIES

GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company. For more information, visit http://www.globalfoundries.com.

 

About Sonics, Inc.
Sonics, Inc. (San Jose, Calif.) is the trusted leader in on-chip network (NoC) and power-management technologies used by the world’s top semiconductor and electronics product companies, including Broadcom®, Intel®, Marvell®, MediaTek, and Microchip®. Sonics was the first company to develop and commercialize NoCs, accelerating volume production of complex systems-on-chip (SoC) that contain multiple processor cores. Based on the ICE-Grain™ Power Architecture, Sonics’ ICE-G1™ is the industry’s first complete Energy Processing Unit (EPU), which enables rapid development of SoC power management subsystems. Sonics is also a catalyst for ongoing discussions about design methodology change via the Agile IC Methodology LinkedIn group. Sonics holds approximately 150 patent properties supporting customer products that have shipped more than four billion SoCs. For more information, visit sonicsinc.com, and follow us on Twitter (@sonicsinc) and LinkedIn.

wafer sort feature

The Ultimate Guide to Wafer Sort

You may have heard of wafer sort or wafer testing, which is a part of the testing process performed on silicon wafers. Wafer sort is a simple electrical test, that is perform on a silicon die while it’s in a wafer form. Wafer sort’s main purpose is to identify the non-functional dies and thereby avoiding assembly of those dies into packages. In many cases, wafer sort is a simple and quick test that focuses on a few electrical parameters that are most likely to fail.

 

Wafer testing is performed during IC production on every wafer and every silicon die. Otherwise, there could be defective semiconductor dies that will go through the assembly process and therefore lead to unnecessary expenses at the end of the manufacturing process.

 

IMG_0592_1

Photo: Probe Card (credit: Synergie-CAD)

 

One can imaging wafer sort as a financial decision that depends on yield, volume and packaging cost. But in some cases, companies perform wafer sort to monitor the silicon foundry yield. This feedback is then feedbacked to the fab to further optimize the silicon manufacturing process and hence improve the process yield.

A digital wafer map is attached to each wafer that has been tested to label the passing and non-passing dies.

 

How the Wafer Sort Works

 

Called by different names such as the Electronic Die Sort (EDS), Circuit Probe (CP), and the Wafer Test (WT), This is the testing performed on the wafer or part of the semiconductor that carries the internal circuitry. Because the circuitry is so small, visual detection of any defects is virtually impossible. So, the testing itself is performed using specific equipment after the wafer has been created.

The wafer testing is done just before it is sent to the die packaging phase. The integrated circuits that are found on the wafer are checked for defects. The process uses test patterns to find any defects and thus eliminate the wafer from the next step in the process. The testing itself is performed by an ATE that has a wafer prober.

 

What is a Wafer Prober?

 

This is the device or machine that carries out the functions of the wafer sort or testing of the integrated circuits. How it works is rather simple. During the testing process the probe card which consists of several contacts that are microscopic in nature are located inside the wafer prober when the wafer itself is positioned for electrical contact. The wafer is mounted on what is known as a wafer chunk to keep it in position. The hold is vacuum-sealed which means that it is strong, but temporary so that another wafer can quickly be moved into position once the testing is over.

 

IMG_1743

Photo: Probe Card (credit: Synergie-CAD)

 

When each die has been tested electronically by the prober, it moves to the next die where another line can be tested. The prober will load and unload the wafer from the carrying device. Plus, it is equipped with optics for automatic pattern recognition so that the wafer is aligned properly for the testing process. That way the testing can be performed with the utmost accuracy and it ensures that a failure of any test is not due to the wafer being incorrectly aligned.

 

The contact pads on the wafer are touched by the tips of the needles from the wafer prober. This allows electricity to be properly conducted through the wafer which if successful completes the test so that the next line or circuit can be tested. However, if the electrical test does not pass through, the wafer is then moved from the manufacturing process for separate testing to ensure that it is defective.

 

IMG_1257

Photo: Probe Head Cantilever (credit: IPhone)

 

The wafer prober can also handle multi-die packages like the System in Package (SiP) or the Stacked Chip-Scale Package (SCSP) thanks to the use of non-contact probes. This allows for the proper identification of the Known Tested Die (KTD) as well as the Known Good Die (KGD) which are vital to increasing the yield of the overall system.

 

Additional Testing

The ATE will also test circuitry along the scribe lines. Performance of the device can be rated when using line test structures. There are companies that get a good amount of information by using this process. There are some dies that include internal spare resources that are used for repairs such as found on flash memory IC. If some test patterns are not passed, the additional resources available can be used.

 

 

Untitled

Photo: Probe Head Vertical (credit: Synergie-CAD)

 

 

If there is no redundancy of the die that has failed in certain tests, then it will be discarded as useless. During the testing process, circuits that do not pass electricity are marked with a small ink dot located in the middle or the wafermap will store the information of failed or inactive circuits.

 

What is a Wafermap?

This is a map that reveals the dies that are passing and non-passing using bins. The bin itself will be defined as either good or bad die. The wafermap will then be sent electronically to the assembly house which only picks up passing dies by choosing the bin number that contains good dies.

In the past, the good dies were marked by ink dot, but this process is not common anymore. The use of ink dots allows for visual inspection as the operator can now disqualify a die based on the ink dot. While only dies that pass all the test patterns are used, there are cases in which one that did not pass all the test patterns can be incorporated if their flaws do not significantly interfere with the device where it will be placed.

 

After IC Packaging

The packaged chip will be tested another time during what is known as the IC phase. This testing process is very similar, if not actually the same as the original wafer test approach. While this might be seen by some as redundant, it does serve as an extra step that can catch a defects in the assembly process, for example, missing bumps or wirebonds.

This double-check helps keep defective dies from being sold or used in devices which creates considerable cost in detecting and replacing. However, there is considerable cost in the testing process, so it is not surprising that some companies that are producing a high yield of dies will skip testing altogether and risk blind assembly for greater efficiency.

 

Find here a list of IC testing companies.

dolphin1

Dolphin Integration Receives Open-Silicon’s Award for the Emerging IP Partner of the Year 2016 in the Low Power IoT Ecosystem

The industry’s focus on battery-powered devices sets new expectations in terms of energy saving for a wide range of applications such as IoT, wearables and wireless MCUs. Meeting the underlying low-power challenge requires a new class of silicon IPs to enable unmatched power consumption figures and new IoT SoC architectures leveraging operating modes with reduced power consumption. In addition, advanced techniques are needed for SoC integration to secure and facilitate physical implementation of power domains.

 

dolphin1

 

Dolphin Integration is the first silicon IP vendor to provide a complete offering for minimization of the power consumption of IoT SoCs, both in sleep and active modes. Its consistent low-power and high-density offering covers:

 

Open-Silicon is a leading provider of turnkey custom SoC design and manufacturing solutions, with a solid track record of successful silicon IP integration from diverse IP vendors. Through this collaboration, Open-Silicon typically sources foundation IPs, possibly with some fabric IPs as well, and the end-customer sources relevant feature IPs and fabric IPs to meet the low-power architectural design challenges. Open-Silicon then performs the SoC integration of the of the whole design, physical design, and delivers fully tested silicon parts to the end-customer.

 

Dolphin Integration is a leading silicon IP provider for low-power IoT SoCs. In view of the growing demand for low power consumption in IoT devices, we intend to leverage the unique solutions offered by Dolphin Integration to meet the challenges of our IoT customers,” said Elias Lozano, Sr. Director of Business Development and IP Solutions at Open-Silicon.

 

As contributors to the TSMC Ecosystem, Open-Silicon and Dolphin Integration are natural partners to answer the growing needs for low-power IoT ASIC architectural innovation and right-on-first-silicon physical implementation.

Dolphin Integration is proud to receive from Open-Silicon the award for the emerging IP Partner of the Year 2016 in the Low Power IoT Ecosystem

 

We are proud to receive this award which recognizes our capability to offer true-to-need semiconductor IPs for the low power IoT ecosystem. Our customers have turned their attention to our unique solutions and techniques, proven right-on-first-pass with a demochip at TSMC 55 nm, for reaching the lowest power consumption.”, said Gilles Depeyrot, CEO of Dolphin Integration.

 

I want more information about Dolphin Integration’s offering

 

About Open-Silicon

 

Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed over 300 designs and shipped over 125 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world.  www.open-silicon.com

 

About Dolphin Integration

 

Dolphin Integration contributes to “enabling low-power Systems-on-Chip” for worldwide customers – up to the major actors of the semiconductor industry – with high-density Silicon IP components best at low-power consumption.

“Foundation IPs” includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. “Fabric IPs” of voltage regulators, Power Island Construction Kit and their control network MAESTRO enable to safely implement low-power SoCs with the smallest silicon area. They also star the “Feature IP”: from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.

 

Over 30 years of experience in silicon IP components make Dolphin Integration a genuine one-stop shop addressing all customers’ needs for low-power and multimedia IP requests.

It is not just one more supplier of Technology, but the provider of the Dolphin Integration know-how!

automotive

Faraday: World’s First ISO 26262 Certified ASIC Service Company

Hsinchu, Taiwan — Jan. 19 2017 — Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, has received the certificate of ISO 26262 (Road vehicles-functional safety) from SGS-TÜV Saar on its design development process. Faraday is the first ASIC design service company in the world approved to ISO 26262; it demonstrates that Faraday is capable of implementing the automotive functional safety standard on its hardware design from product concept to mass production.

 

To penetrate the automotive application market, Faraday has built a taskforce team of AFSP (Automotive Functional Safety Professional) certified experts, including R&D and technical account service managers, responsible for developing automotive safety techniques. Complete IP functional safety mechanism and documentation are established and integrated into Faraday’s ASIC design service.

 

“We are happy that Faraday‘s design development process is certificated to ISO 26262; it proves that Faraday is able to provide customers with designs compliant to the safety standard,” said Steve Wang, President of Faraday. “We take functional safety as the highest priority on automotive design development. Faraday will carry out respective activities in each phase of the safety life cycle and continuously invest in our safety management,” he added.

 

“Automotive application is one of the fastest-rising semiconductor market segments but with relatively higher entry barrier. In order to shorten the time to market, Faraday pioneered the ASIC service industry to get certified to ISO 26262 on its design development process. We believe it will greatly help Faraday to win in the high-end automotive application market,” said Steven Chiou, Director of SGS.

 

About Faraday Technology Corporation

Faraday Technology Corporation is a leading ASIC design Service and IP provider. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, MPEG4, H.264, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed on the Taiwan Stock Exchange, ticker 3035. For more information, please visit t:www.faraday-tech.com

einfochips

eInfochips Positioned in the Leadership Zone for Semiconductor Services

eInfochips, a leading Product Engineering and Software R&D services firm, recently announced that the company was rated in the “Leadership Zone” for Semiconductor services by Zinnov, in its annual “Zinnov Zones 2016 PES” ratings. eInfochips was also recognized under “Execution Zone” for Aerospace, Industrial Automation, Medical Devices, and Consumer Software.

 

 

“We are very happy to be recognized in the Leadership Zone by Zinnov. The product engineering services market is evolving rapidly to cater to newer technological needs in enabling smarter systems and connected ecosystems. With capabilities from sensors integration to cloud deployments to analytics, and with IPs and accelerators in DevOps, remote device management, and IoT & cloud frameworks, we have been enabling our customers to gain significant competitive advantage,” said Abhishek Binaykia, Associate Vice President of Marketing at eInfochips. “Our in-depth service offerings and platform driven approach positions us well to serve and co-create the next generation IoT products with top solutions and product companies around the world.”

 

 

Zinnov Zones is an annual rating, which rates Service Providers based on their competencies and capabilities. It has become one of the most trusted reports globally, for both enterprises and service providers to better understand the vendor ecosystem in multiple domains. It ranks global players on the basis of their R&D Practice Maturity, Breadth, Innovation and Ecosystem Connect. For more information on Zinnov Zones 2016 PES, please click here.

 

 

About Zinnov:
Founded in 2002, Zinnov is headquartered in Silicon Valley and Bangalore. In over a decade, they have built in-depth expertise in engineering and digital practice areas. They assist their customers in effectively leveraging global innovation and technology ecosystems to accelerate innovation and digital transformation. With Zinnov’s team of experienced professionals, they serve clients in Software, Automotive, Telecom & Networking, Semiconductor, Consumer Electronics, Storage, Healthcare, Banking, Financial Services & Retail verticals in US, Europe, Japan & India.

 

Visit at http://www.zinnov.com. To request information, contact Jaya Shukla at media(at)zinnov(dot)com

 

 

About eInfochips:

eInfochips is a product engineering and software R&D services company with over 20 years of experience, 500+ product developments, and over 40M+ deployments in 140 countries across the world. Today, 60% of its revenues come from Fortune 500 companies and 80% from solutions around connected devices. From silicon to embedded systems to software, from deployment to sustenance, they map the product journey of their customers. The company has the expertise and experience to deliver complex, critical, and connected products across multiple domains, for projects as small as a one-time app development to a complete turnkey product design. With its R&D centers in the USA and India, eInfochips continuously invest and fuel innovations in the areas of Product Engineering, Device Lifecycle Management, IoT & Cloud Frameworks, Intelligent Automation, and Video Management. The company has sales presence in the USA, Japan, and India.

 

Visit at http://www.einfochips.com. To request information, contact Sooryanarayanan Balasubramanian at marketing(at)einfochips(dot)com