Monthly Archives: May 2017

iot

Challenges and Opportunities for the Semiconductor Industry in the IoT

The Internet of Things has become a mainstream technology strategy for businesses looking to accelerate growth in 2017 and beyond. The semiconductor industry isn’t immune to the ongoing IoT buzz, as experts believe that major players will soon abandon the pursuit of Moore’s Law in favor of a wholesome strategy necessitating more powerful chips and reliable IoT applications—an important enabler to a connected world.So, what explains the draw to IoT movement? Most semiconductor companies are motivated by the pursuit of an increased foothold in the technology space, as well as stronger customer relationships that will be fostered owing to their ability to deliver unparalleled customer experiences through IoT solutions. Gaining quality insights and reliability due to integration with analytics and BI data, lowering the node technology costs and reducing investment risks and IP theft are some additional perks in the transition.

 

 

“The demand for billions of things will ripple throughout the entire value chain, from software and services to semiconductor devices,” said Alfonso Velosa, Gartner Research‘s director, in a prepared statement.

 

 

Challenges and Opportunities

 

First of all, with the ongoing pace of IoT development, semiconductor companies are set to benefit from newer innovations across the technology value chain. They can gain more traction by providing comprehensive solutions beyond semiconductor solutions, which include hardware design, software and systems integration for products and applications. The digitization of sensors, wearables, and networking technologies increases the demand for semiconductor products.

 

 

As the cloud economy becomes mainstream in the IoT era, semiconductor companies need to continuously innovate to drive connectivity across the IoT value chain. Additionally, IoT-connected products and applications would require chips with an ultra-small form factor, low power consumption and wireless connectivity options.

 

 

With the increased adoption of IoT sensor products like smart watches and glasses, as well as smartphones and other wearable devices, the semiconductor industry drives MEMS/NEMS sensor platforms with the power advantages of lower technology nodes and increased functionality on a single small form-factor die.

 

 

As the technology node shrinks, engineers have been trying to figure out the method to manage placement density and high memory count. At this time, lower geometry design becomes a major area of focus and tape-outs using advanced technology. Chip size has continued to decrease from year to year, from 90 nanometers to 65, 40, 28, 14 and 7 nanometers. Read here how and why a leading industry player in complex ASIC solutions opted for a 16-nanometertechnology node for its SDN functionality.

 

 

Power consumption is another major concern during functional testing, especially facing lower design technology. As chip size shrinks, density tends to increase to nearly a million gates on a single chip, and power dissipation occurring in the chip due to leakage will become very significant. In order to reduce the loss of power, several leakage power minimization techniques have been developed. You can read more here about one such power leakage optimization technique in systems-on-chips.

 

 

The above are some of the trends and challenges faced by semiconductor players in IoT transformations. To know more about the role of the semiconductor industry in the Internet of Things, watch the following video: “Role of Semiconductors in the IoT Era of Networking Industry.”

 

 

Komal Chauhan works in the Marketing Department at eInfochips, where she supports digital marketing and content writing activities in semiconductor and IoT applications that help companies to take advantage of product-engineering services in a dynamic market. With the encouragement of friends and colleagues, Komal started writing on evolving technology trends. She can be reached at marketing@einfochips.com, or you can connect with her on LinkedIn.

 

 

Note: This article was originally published in IoT Journal.

 

 

Click here to see eInfochips’s profile page on AnySilicon.

watch

Programmable Battery Charger IP Cores For SoC Applications

Since its inception in 2008, Chipus has been developing a series of analog power management IP cores, including linear regulators, power-on resets, ultra low power references (voltage and current), and power management units, using various architectures, and employed by customers worldwide in various application areas.

 

Chipus is now building out its power management offerings by expanding its line of battery charger IP cores, designed for modern mobile and IoT applications, where battery powered solutions are ubiquitous.

 

In 2013, Chipus has launched its first linear Li-Ion battery charger IP (CM1711ff) for SilTerra 0.18um CMOS technology. Last year, the second generation (CM1712ff) designed for SilTerra 0.18um BCD technology was announced and a third generation (CM1713ff) is already under development, with release planned for the second half of 2017.

 

Chipus familiy of battery charger IPs consist of a completely integrated, precision Li-ion battery charger IP block (4.2V±1%) suitable for portable applications. They are capable of charging from AC adapters or USB source and can include an internal NTC, among several other important and useful features for SoC integration.

 

Chipus has built a wealth of best practices for Li-ion battery management, which differentiates their battery chargers and enables advanced capabilities. This includes integrated protection against overheating of the die and of the battery, over/under voltage, and reverse current protection.

 

As an example, with autonomously adaptive charging modes and easily reconfigurable maximum charge current, Chipus battery charger IPs provide suitable current profiles for different Li-ion batteries guaranteeing their full performance and life span.

 

Main features

  • Programmable charge current: 10mA to 1.5A
  • Easy integration in SoC
  • Integrated power FET
  • Trickle, fast, and constant voltage charging modes
  • Integrated protections (voltage, temperature, reverse current)
  • Charging status flags
  • Easy porting to other technologies

 

For more information about this IP, please refer to the application note “Integrating Chipus Battery Charger IPs into your SoC” that has just been added to Chipus website (http://www.chipus-ip.com/family/highlights/) or write to ip@chipus-ip.com.

 

About Chipus

Chipus Microelectronics (www.chipus-ip.com) is a semiconductor company focused in the development of low-power, low-voltage, analog and mixed-signal intellectual property (IP) blocks for integrated circuits (ICs) and systems on chip (SoCs).

 

Relying on a strong experience in power management and data converters, the company has more than 150 IP blocks in process nodes from 40nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has licensed such IPs and provided associated IC design services with firm commitment and flexible client support to customers worldwide (South and North America, Europe, and Asia).

 

Headquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales teams in both USA and Europe. For further information, do not hesitate to contact us at ip@chipus-ip.com.

 

Checkout Chipus’s profile page on AnySilicon: http://anysilicon.com/vendors/chipus-microelectronics/

apple-icon-apple

Apple is working on an AI Chip (IC)

Apple began relatively early with artificial intelligence software when it introduced Siri in 2011 – a tool that allows users to activate their smartphones with voice commands. Now, the electronics giant is bringing artificial intelligence to ICs.

 

Apple is working on a processor specifically designed for artificial intelligence tasks, according to a related source. The chip, known in the company as the Apple Neural Engine, will improve how the company’s devices deal with tasks that will otherwise require people’s intelligence – such as face recognition and speech recognition, said the associate, who wanted to remain anonymous. Apple declined to comment.

 

 

Apple engineers are trying to fill gaps with their Amazon and Alphabet counterparts in the field of artificial intelligence, which has been on the rise recently. Siri gave Apple an initial voice recognition advantage, but since then competitors have been able to apply artificial intelligence to their products, such as Amazon’s ECho or Google Home.

 

 

An artificial intelligence processor will enable Apple to introduce more advanced capabilities to its devices, especially for autonomous cars and virtual reality devices. “The two areas that Apple is betting on in the long term require artificial intelligence,” said Gene Munster, a former Apple analyst and co-founder of venture capital firm Loop Ventures. “In the heart of the imaginary reality and the autonomous car is artificial intelligence,” he says.

 

 

Apple’s devices now have a two-chip system designed to process AI: the main processor and the graphics chip. The new chip will enable the company to deliver these tasks to a special module designed for its needs, and will enable improved performance of the battery.

 

 

Apple is following in the footsteps of other manufacturers who have already developed special artificial intelligence ICs: Qualcomm’s Snapdragon chip has a module for artificial intelligence tasks; And Google announced its first chip, Tensor (TPU), last year. This chip is located in Google’s data centers to improve search and image recognition capabilities.

 

 

peacock

Alma Technologies Introduces an Online Tool for Comparison of Image Compression Standards as Implemented by our IP Cores

An online tool for back-to-back comparison of the image compression standards implemented by our IP cores is now available on our website.

 

The Bit Accurate Models of the respective image compression cores are used to encode / decode a user supplied test image, in order to evaluate and compare their actual performance.

 

This tool is very useful for evaluating the compression efficiency at various compression ratios. The user uploads a test image, sets the target compression ratio and the tool compresses and decompresses this image with all supported algorithms. The reconstructed image, the achieved compression ratio, the PSNR and the Structural Similarity (SSIM) metrics are put together in comparison graphs for easy evaluation of each image compression standard. For lossless algorithms where the output image is bit-by-bit identical to the input image, the achieved compression ratio is displayed only.

 

The following standards as implemented by our IP cores are compared back-to-back:

 

Lossy mode Compression Standards
JPEG vs JPEG 2000 vs CCSDS 122.0-B-1 vs H.264 All-Intra

 

Lossless mode Compression Standards
JPEG-LS vs JPEG 2000 vs CCSDS 122.0-B-1

 

Try the tool for back-to-back comparison of image compression standards in the following link:

https://www.alma-technologies.com/page.CompressionComparison

 

Click here to see more products from Alma Technologies.

car

2017 Automotive Semiconductor Market on Pace for Record Year

Electronic systems that improve vehicle performance; that add comfort and convenience; and that warn, detect, and take corrective measures to keep drivers safe and alert are being added to new cars each year. Consumer demand and government mandates for many of these new systems, along with rising prices for many IC components within them, are expected to raise the automotive semiconductor market 22% this year to a new record high of $28.0 billion (Figure 1).

Over the past several years, the global automotive semiconductor market has experienced some extraordinary swings in growth.  After increasing 11.5% in 2014, the automotive semiconductor market declined 2.5% in 2015, but then rebounded with solid 10.8% growth in 2016.  It is worth noting that the sales decline experienced in 2015 was primarily the result of falling ASPs across all the key automotive semiconductor product categories—microcontrollers, analog ICs, DRAM, flash, and general- and special-purpose logic ICs, which offset steady unit growth for automotive ICs that year.

Figure 1

However, in the second half of 2016, steadily rising ASPs (along with demand for the new automotive systems) helped return the automotive IC market to double-digit growth. In 2017, exceptionally strong increases in DRAM and flash memory prices are expected to help drive the total automotive IC market to an extraordinary increase of 22.4%.
IC Insights recently revised its IC market outlook for 2017 and now shows DRAM average selling prices rising 50% in 2017, NAND flash ASPs increasing 28%, and the average selling price for automotive special-purpose logic devices increasing 34%. these strong ASPs gains, coupled with ongoing system demand, are driving the strong automotive IC market growth this year (Figure 2).


Figure 2

 

Collectively, microcontrollers, analog, standard logic, and memory ICs used in automotive applications accounted for only about 8% of total IC marketshare by system type in 2016, but that share is forecast to increase to more than 10% in 2020, when automotive is expected to become the third-largest end-use category for ICs, trailing only the communications and computer segments.   Through 2020, IC Insights anticipates that advanced driver-assistance systems (ADAS) will be the biggest user of automotive ICs.  Various ADAS systems are currently helping cars and drivers remain safe on the road and they are proving to be essential building blocks to semi autonomous and autonomous vehicles that are being proposed for the next decade.

 

More Information Contact

For more information regarding this Research Bulletin, please contact Brian Matas, Vice President at IC Insights. Phone: +1-480-348-1133, email: bmatas@icinsights.com

daisychain

IC Test Flow For Advanced Semiconductor Packages

Higher bus speeds and lower power consumption are design criteria for most modern digital electronic products. Packaging solutions that provide higher bus speeds at reduced power per bit ratios require design techniques that shorten the distance between chips (to reduce drive currents) and use wider data buses (with finer line-space traces). Through Silicon Vias (TSVs) solve these challenges but require new test strategies to qualify these designs while keeping quality and cost within design targets.

 

The IC Test Issue

Electrical testing of TSVs can only be performed after the back-grind and etch processes expose the TSVs – a task that is usually performed at the Outsourced Assembly, and Test (OSAT) supplier. Figure 1 illustrates this dilemma. Therefore, when a TSV interposer wafer leaves the foundry, the quality of the TSVs remains unknown until it is processed at the OSAT.

Within a package, the functions of the TSVs can vary widely. Basically, these connections may be used to carry DC current to power the chip or carry high-speed signals for input /output (I/O) pins or provide low-impedance paths which connect the die to the ground plane. Based on their functions, specific tests need to be performed to verify TSV functionality. Furthermore, TSVs need to undergo characterization tests such as stress and electromigration to quantify their long-term reliability.

 

Exploring Alternatives

Defects in TSV structures are potentially caused during their manufacture at the foundry or during the TSV “reveal process” at the OSAT. During the fabrication of TSVs, micro-voids, due to quasi-conformal plating, might lead to weak-opens in TSVs, while ineffective removal of the seed layer might lead to shorts between TSVs.

Much effort has been expended in testing the quality of an interposer after active-die or dies attachment. These techniques include Built-In-Self-Test/Diagnosis/Repair (BIST/D/R), Reduced Pad-Count Testing (RPCT), Test Data Compression (TDC), and more. If a problem with a certain path is identified, these approaches rely on redundant resources that can be used to restore device functionality. However, problem identification occurs after an expensive application specific integrated circuit (ASIC) has been attached to the interposer/substrate. If these techniques are used when the first die is attached on a multi-chip module, they can detect problems early in the assembly process. At this point, testing can identify if the problem can be fixed by using an alternate electrical path, apply the fix, and then verify the fix or if no redundancy exists, fail the subassembly before more dies are added, reducing scrap costs.

Figure 1: Interposer wafer with TSVs as received from fab.

 

Often, the ASIC used with the TSV interposer is a large die, which typically is a high-end processor, with about 60% to 70% of the dies per wafer meeting the performance criteria of the final package. Utilizing one of these premium ASICs to identify a fault in the interposer is an expensive option and not the optimal use of a scarce resource – the ASIC.

 

To achieve the lowest scrap cost, methods of testing the interposer die before it is attached to a substrate should be explored. An easier approach, but at a slight higher cost, would be testing the interposer vias after it is attached to the substrate.

 

Alternatively, the interposer designer can use multiple redundant vias “n+1”, where “n” represents the number of redundant vias for a single vertical connection. This method works well when there is adequate space under the ASIC, however, as the size of the die shrinks, the number “n” tends to zero i.e., no redundancy, leaving space only for a single via per connection. Furthermore, current trends in the reduction of pad size and pitch might limit the ability to place redundant TSVs for each connection. Therefore, it is necessary to establish robust manufacturing methods for TSVs that result in ultra-high yields.

 

Case STUDY: TSV supplier qualification

 

After analyzing potential sources for defects, test techniques (including optical and electrical methods), and test location (foundry or OSAT) alternatives, a project was initiated to confirm the results of the analysis and verify acceptable qualification approaches. As shown in Figure 2, a test vehicle was defined which resembles the final product interposer and allows its use for both interposer vendor qualifications as well as the package-assembly process qualification. This would imply that the test vehicle and the final product would share the same physical size, quantity, and location of the micro bumps/controlled collapse chip connection (C4s). A good practice is to have the test vehicle wired with multiple daisy chain test structures, where each structure is a set of TSVs grouped by their position on the die (e.g. GPU1 NW Corner) with the goal for the daisy chain to flow through every single TSV in that area. Creating regions helps in the failure analysis team to zero-in on the fault area.

Figure 2: TSV interposer test vehicle.

 

Interposer Designed for Test

 

As shown in Figure 2, the end product interposer design was translated into a test vehicle. With a micro bump size within the sub 25-µm range and a C4 size of around 80 µm, the final product accommodated approximately 75,000 micro bumps and about 25,000 C4s.

 

For versatility, the test structures were designed to break the daisy chains into sub-chains. The electrical path for each sub-chain would be completed by a metal layer on the interposer. Additionally, the sub-chains would be joined to form the full chain using metal layers from the top-die test vehicle, as shown in Figure 3.

Figure 3: Daisy chain top die (red) and interposer (blue).

 

Additionally, the test vehicle was used to study the impact of stress and strains which the interposer die will experience when the package is fully assembled (i.e., with top dies attached, under-filled, stiffener ring attached, and the complete assembly over-molded, etc.), therefore, the location of the daisy chains was critical. Daisy chain structures were placed in areas where the large mechanical stress and strain affect the reliability of the TSV structures. Additionally, the test vehicle incorporated strain gauge structures, which was used to measured and monitor stress/strain on the package through the assembly process.

 

Daisy Chain Resistance Selection

 

The designer has to choose the resistance values of the daisy chains bearing in mind the metrology. From an equipment perspective, when the number of networks to be measured is below two dozen, a traditional ohmmeter can be used, however, when it exceeds a hundred, the choice of equipment switches to automatic test equipment (ATE) or open-short testers. The metrology ATEs use to test for opens or short is called force current, measure voltage (FIMV). They achieve this by setting the clamp voltage to 3V (adjustable) and forcing a current of 100 µA, then measuring the voltage between the pin under test and ground. The supply and ground pins are connected to ground. A voltage measurement between 0.2V to 0.8V (diode forward voltage) would indicate that the pin under test is connected to the silicon. An open would be indicated by a measurement of clamp voltage and a short (to VDD or GND) by a 0V reading.

 

 

Figure 4: Test list, C4 pads and test limits.

ATE machines complete the measurement in a couple of milliseconds and are not expected to provide an accurate resistance measurement, rather just provide a pass or fail result. Thus it is best for the designer to maintain the daisy chain resistance values between 300 ohms and 3 kilo ohms.

Furthermore, most ATE tester configurations have up to 2500 pins available for test; therefore, the designer must balance the lengths of the daisy chain and the nets to within the tester pin counts.

 

Vendor Qualification – Test Metrology and Apparatus

 

One of the key requirements for the evaluation was to provide quick feedback on the quality of the interposer; therefore, it was decided co-locate test with the assembly line, limiting the equipment choice. The prober available on the assembly line was a semi-automatic PA300 with 12-inch wafer capability. The test setup, probe card, and test program had to be simple and intuitive for an operator to use and provide downstream feedback.

Figure 5: Probe locations for test vehicle.

 

To limit the size of the experiment, seventeen test structures (Figure 4) were selected, located symmetrically in the four quadrants of the die (Figure 5). A cantilever probe card was used with four-wire capability, with two probes (force+ and sense+) landing on daisy chain input C4 bump, and two (force- and sense-) on the output C4 as seen in Figure 6.

 

Figure 6: Cantilever probe card – zoomed in.

 

The test condition was “DC” only – i.e., resistance testing. High-frequency performance was done separately using 50-ohm co-planar waveguide test structures on the interposer and performed using a network analyzer. To avoid the additional, reflow step, the balanced contact force (BCF) was tuned to limit the damage on the C4 during probe, see Figure 7.

Figure7: Scrub mark overdriven to show force/sense.

 

Using the interposer design information such as the trace width, thickness, and the daisy chain length, resistances for each daisy chain structure were computed, creating the test specification and the pass-fail limits. The test equipment consisted of four relay boards that switched the four-wire lines from the two Keithley 2400’s source-measure units to two probe transition boards that mapped the measurement point to the probe needles as shown in Figure 8.

 

Figure 8: Test setup.

 

Since a semi-automatic prober was used, the interposer wafers that were mounted on carriers were loaded manually on to the PA300 prober. The optical character recognition (OCR) feature was not available on the prober, so all carrier wafer IDs were manually recorded and later mapped to the interposer ID. Figure 9, shows an interposer wafer mounted on a carrier.

Figure 9: Interposer wafer on carrier.

 

Test Data Resistance Measurements Interposer Rev# 1

 

In the first revision of 25 interposer wafers, the test data was collected and the measurement showed consistency across all wafers (Figure 10). Since the test structures chosen were symmetrical (Figure 5), it provided a way to compare the test structure results across the four quadrants of each die and with the wafer as a whole. From the histograms generated, the consistency within the datasets proved that both the measurement metrology and TSV manufacturing techniques were stable. Failures were observed at the outside ring of the interposer wafer (Figure 10). Within the die these failures were not limited to a particular area or test structure, but observed randomly distributed across the test structures.

Figure 10: Wafer map and measurement histogram.

 

An attempt was made to measure the leakage currents in the order of a few femtoamperes (fA) on some of the test structures, but the 6-foot-long cables that connected the transition board to the probe card (Figure 11) proved to have a higher leakage than the 100 fA target measurements.

Figure 11: Open-circuit leakage measurements.

 

This measurement could detect leakages in the order of a few of microamperes, identifying weak shorts. However, since substrates are considered “bad” only when its leakage currents exceeded 100 µA, setting fail criteria for the interposers a couple of orders of magnitude higher than the substrate it attaches to, would result in over rejection of interposer die. As a result, investing in a test setup to measure femtoamperes of leakage did not justify the expense and was found unsuitable for high-volume production.

 

Test Data Resistance Measurements Interposer Rev# 2

 

After presenting the first round of measurement data to the interposer supplier, changes were made to the TSV fabrication process and a second revision of interposer wafers were provided to test. The results of the second round of test data showed a huge improvement in the quality of the interposer. In version 1 of the interposers, out of the 28,475 test structures, there were approximately 276 failures. In the second version, for the same number of test structures the failures dropped to 9, a clear indication that process improvements/revisions could improve TSV yield.

 

TESTING IS OPTIONAL

 

While electrical test of interposers adds a level of confidence to the quality and connectivity of the die, it also adds cost and consumes real estate. Armed with test data, and mathematical models, we can conclude with high confidence that electrical testing of TSVs are not required after an interposer vendor is qualified and produces high-yielding wafers.

 

When the test step is eliminated, adding 100% automatic optical inspection (AOI) into the interposer fabrication process prevents blind-assembly builds. Furthermore, the AOI step acts as a process watchdog which can quickly identify manufacturing process drift, sustain yields and provide high-quality interposers without test.

 

 

 

REFERENCE:

[1] Gerard John, “A Practical Approach to Test Through Silicon Vias (TSV),” IWLPC 2016, Oct.18-20, 2016

 

_____________________________________________________________________________________

This is a guest post by Gerard John, Senior Director Advanced Test, Amkor Technology Inc., Tempe, Arizona, USA,

Gerard.john@amkor.com