Monthly Archives: July 2017

GLOBALFOUNDRIES and VeriSilicon To Enable Single-Chip Solution for Next-Gen IoT Networks

GLOBALFOUNDRIES and VeriSilicon today announced a collaboration to deliver the industry’s first single-chip IoT solution for next-generation Low Power Wide Area (LPWA) networks. Leveraging GF’s 22FDX® FD-SOI technology, the companies plan to develop intellectual property that could enable a complete cellular modem module on a single chip, including integrated baseband, power management, RF radio and front-end module combining both Narrowband IoT (NB-IoT) and LTE-M capabilities. The new approach is expected to deliver significant improvements in power, area, and cost compared to current offerings.


With the proliferation of connected devices for smart cities, homes, and industrial applications, network providers are developing new communications protocols that better meet the needs of emerging IoT standards. LPWA technology takes advantage of the existing LTE spectrum and mobile infrastructure, but focuses on delivering ultra-low power, extended range, and much lower data rates for devices that transmit small amounts of infrequent data, such as connected water and gas meters.


The two leading LPWA connectivity standards are LTE-M, which is expected to get traction in the U.S. market, and NB-IoT, which is gaining ground in Europe and Asia. For example, the Chinese government has targeted NB-IoT for nationwide deployment over the coming year. The combination of these two technologies is expected to push cellular M2M module shipments to nearly half a billion by 2021, according to ABI Research.


GF and VeriSilicon are developing a suite of IP to enable customers to create single chip cost- and power-optimized solutions for worldwide deployment, based on a dual-mode carrier-grade baseband modem with integrated RF front-end module. The design will be fabricated using GF’s 22FDX process, which leverages a 22nm FD-SOI technology platform to provide cost-effective scaling and power reduction for IoT applications. 22FDX is the only technology that allows efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. This integration is expected to deliver more than an 80 percent improvement in both power and die size compared to today’s 40nm technologies.


“Our 22FDX technology is perfectly positioned to support the explosive growth of low-power, battery-operated IoT devices,” said Alain Mutricy, senior vice president of product management at GF. “We are especially excited about the opportunities presented by the China market, which is leading the way with a nationwide commitment to IoT and smart cities. This new initiative expands on our long standing relationship with VeriSilicon—an important partner helping us build an FD-SOI ecosystem around our new 300mm fab in Chengdu.”


“Started from more than five years ago, as a Silicon Platform as a Service (SiPaaS) company, VeriSilicon has developed FD-SOI IPs and achieved first silicon success of many chips based on FD-SOI technologies. For IoT applications, besides cost advantages, integrated RF, body bias, and embedded memory, such as MRAM, are the key benefits of FD-SOI technologies beyond 28 nm bulk CMOS.” said Wayne Dai, VeriSilicon Chairman, President and CEO. “Integrated with RF and PA on GF 22FDX, the baseband and protocol stack are being implemented on our energy efficient and programmable ZSPnano that is optimized for control and data flow with powerful low latency, single cycle instructions for signal processing. GF’s new 300 mm fab for FDX in Chengdu and IP platforms such as this single chip solution for integrated NB-IoT and LTE-M, will have significant impact on China IoT and AIoT (AI of Things) industries.”


GF and VeriSilicon expect to tape out a test chip based on the integrated solution, with silicon validation in Q4 2017. The companies plan to pursue carrier certification in mid-2018.


About GF:

GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company. For more information, visit


About VeriSilicon

VeriSilicon Holdings Co., Ltd. (VeriSilicon) is a Silicon Platform as a Service (SiPaaS®) company that provides comprehensive System on a Chip (SoC) and System in a Package (SiP) solutions for a wide range of end markets including mobile internet devices, datacenters, the Internet of Things (IoT), automotive, industrial, and medical electronics. Our machine learning and artificial intelligence technologies are well positioned to address the movement to “intelligent” devices. SiPaaS provides our customers a substantial head start in the semiconductor design and development process and allows the customers to focus efforts on core competency with differentiating features. Our end-to-end semiconductor turnkey services can take a design from concept to a completed, tested and packaged semiconductor chip in record time. The breadth and flexibility of our SiPaaS solutions make them performance effective and cost efficient alternatives for a variety of customer types, including both emerging and established semiconductor companies, Original Equipment Manufacturers (OEMs), Original Design Manufacturers (ODMs), and large internet/cloud platform companies.


VeriSilicon’s camera-in, display/video out pixel processing platform includes high-fidelity ISP, embedded Vision Image Processor (VIP) with machine learning acceleration, Vivante® low power GPU and high performance GPGPU, Hantro® ultra high definition video codec, and rich featured display controller, which work seamlessly together to deliver best PPA (Performance, Power, Area). In addition, based on our ZSP® (digital signal processor) technologies, HD audio/voice platforms and multi-band/multi-mode wireless baseband platforms including BLE, Wi-Fi, NB-IoT, and 5G provide scalable architectures for both ultra-low power and extremely high performance applications. Our value-added mixed signal IP portfolio enables energy efficient Natural User Interface (NUI) platforms for voice, gesture and touch.


Founded in 2001 and head-quartered in Shanghai, China, VeriSilicon has over 600 employees with five R&D centers and nine sales offices worldwide.

Sankalp Semiconductor to hire 300 engineers


Sankalp Semiconductor a design service company offering comprehensive digital & mixed signal SoC solutions, today announced its plan to hire 300 engineers in the next 12 months. Sankalp plans to hire engineers for its India design centers in Bangalore, Hubli and Kolkata. The hiring plans will enable Sankalp to meet demands from its existing and new customers in North America, Europe and Asia. Sankalp provides services in the digital, analog & mixed signal, custom layout and technology foundation space. These services have enabled customer to build semiconductor solutions for automotive, consumer, IoT, networking markets.


“We have doubled the capacity of our Kolkata design center, and have aggressively started recruitment for all our design centers.” Said Nagaraj Azhakesan, COO, Sankalp Semiconductor. “We are witnessing excellent growth in digital and mixed signal design services space and will be hiring a health mix of experienced and fresh engineering talent.”


The new Kolkata facility will have an additional seating capacity for 100 engineers. The Kolkata center will continue to execute and focus on complex mixed signal design projects. Sankalp’s multisite design center model has enabled the company to attract talented engineers from various cities. All the fresh engineering graduates go through a structured 6 months on the job training program that enables them to come up to speed with Sankalp’s customer delivery and quality standards.


About Sankalp Semiconductor

Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including digital, analog, high-speed physical interface IP, Embedded Memory Compiler and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System-on-Chip. Sankalp Semiconductor is based in Sunnyvale, California, with multiple development and services centers in India, Canada and Germany.


Contact Information:
Eklovya Sharma
Sankalp Semiconductor
+91-9879048571 (Mobile)

Constrained Random Verification flow strategy

The explosive growth of cellular market has affected the semiconductor industry like never before. Product life cycle have moved to an accelerated track to meet time to market. In parallel, engineering teams are in a constant quest to add more functionality on a given die size with higher performance and less power consumption. To manage this, the industry adopted reusability in design & verification. IPs & VIPs have carved out a growing niche market. While reuse happens either by borrowing from internal groups or buying from external vendors, the basic question that arises is, whether the given IP/VIP would meet thespecifications of SoC/ASIC? To ensure that the IP serves requirement of multiple applications, thorough verification is required. Directed verification falls short in meeting this target and that is where Constrained Random Verification (CRV) plays an important role.


A recent independent research conducted by Wilson Research Group, commissioned by MentorGraphics revealed some interesting results on deployment of CRV.


In past 5 years –

– System Verilog as a verification language has grown by 271%

– Adoption of CRV increased by 51%

– Functional coverage by 65%

– Assertions by 70%

– Code coverage by 46%


– UVM grew by 486% from 2010 to 2012

– UVM is expected to grow by 46% in next 12 months

– Half of the designs over 5M gates use UVM


A well defined strategy with Coverage Driven Verification (CDV) riding on CRV can really be a game changer in this competitive industry scenario. Unfortunately, most of the groups have no answer to this strategy and pick adhoc approaches only to lose focus during execution. At a very basic level, focus of CRV is to generate random legal scenarios to weed out corner cases or hidden bugs not anticipated easily otherwise. This is enabled by developing a verification environment that can generate test scenarios under direction of constraints, automate the checking and provide guidance on progress. CDV on the other hand uses CRV as the base while defining Simple, Achievable, Measurable, Realistic and Time bound coverage goals. These goals are represented in form of Functional coverage, Code coverage or Assertions.


The key to successful deployment of CDV+CRV demands avoiding redundant simulation cycles while ensuring overall goals, defined (coverage) and perceived (verified design) are met. Multiple approaches to enable this further are in use –

– Run random regressions while observing coverage trend analysis till incremental runs aren’t hitting additional coverage. Analyze coverage results and feedback to the constraints to hit remaining scenarios.

– Run random regressions and use coverage grading to come up with a defined regression suite. Use this for faster turnarounds with a set of directed tests hitting the rest.

– Look for advanced graph based solutions that help you attain 100% coverage with most optimal set of inputs.


To define a strategy the team needs to understand the following –

– Size of design, coverage goals and schedule?

– Availability of HW resources (server farm & licenses)?

– Transition from simulator to accelerator at any point during execution?

– Turnaround time for regressions with above inputs?

– Room to run random regressions further after achieving coverage goals?
– Does the design services partner bring in complementing skills to meet the objective?

– Does the identified EDA tool vendor support all requirements to enable the process i.e. Simulator, Accelerator, Verification planner, VIPs, Verification manager to run regressions, coverage analysis, coverage grading, trend analysis and other graph based technologies.


A sample flow using CRV is given below –







This a guest post by Gaurav Jalan, general chair at DVCON India

HDL Design House and AFuzion Synergy to Enhance DO-254 Projects


Belgrade, Serbia – July 20th, 2017 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, and AFuzion, the safety-critical systems and certification company, have started a collaboration to simplify the complex DO-254 project requirements and reduce overall project time, by relying upon HDL DH’s verification expertize and AFuzion’s DO-254 training and avionics certification services. The collaboration will provide customers with turn-key DO-254 solutions and expertise at any project phase.


The initial phase of any DO-254 project requires in-depth knowledge of the DO-254 standard. AFuzion’s DO-254 training is the world’s largest and provides customers with a solid foundation to commence their DO-254 projects. Another crucial prerequisite is documentation, and AFuzion’s all-new, proprietary DO-254 Templates and DO-254 Checklists facilitate the project continuation.


The most critical part of DO-254 projects is verification, since it provides evidence that the design meets requirements. The use of random verification which improves the quality of the design and enables detecting a greater number of defects in early project stage, while adhering to DO-254 processes is a great challenge. Moving from standard direct-test approach to random verification within DO-254 processes can be very difficult. Also, the project documentation which is required for the complete random verification process has to be in accordance with DO-254 standard as well as checklists. HDL Design House has a proven track record working on numerous projects in the avionics market, including DAL-A and DAL-B criticality levels for all aircraft types.


Finally, AFuzion’s avionics hardware DO-254 Gap Analysis examines the avionic product’s safety, hardware requirements, FPGA/ASIC/PLD design, V&V, tools, and Process Assurance (QA) to assess and leverages compliance to FAA and EASA standards / expectations while lowering DO-254 Costs, especially with HDL’s cost-effective DO-254 verification services.


The synergy between HDL DH and AFuzion offers customers guidance and support throughout the demanding DO-254 projects and enables them to lean on the expertize in design and verification and certification processes at any project stage.


About AFuzion:


AFuzion Inc. is the world’s largest avionics compliance services consultancy specialized in DO-254 and DO-178C training, mentoring, project ramp-up and certification/compliance. AFuzion’s actual engineers created the world’s first public training in DO-178C/DO-254 and have since trained over 13,000 engineers/managers in 35+ countries: more than all the world’s competitors combined. AFuzion has performed over 55 DO-254 Gap Analysis and over 130 DO-178, DO-278A, and ARP4754A Gap Analysis – also more than all competitors combined. AFuzion’s DO-254 Plans, Checklists, and Templates are world class and used by dozens of companies worldwide. AFuzion personnel also principally authored the world’s best-selling book on DO-254 and DO-178C along with dozens of avionics development whitepapers available for free download at



About HDL Design House:


HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 140 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). HDL DH joined the ARM® Approved Design Partner program, through which leading SoC design houses are recognized by ARM as accredited partners in specific technologies and activities. For more information, please visit



Negative Delays aren’t so Negative after all !

You read the term “negative delay” and your engineer mind goes racing creating science fictions – time machine, time generator, non-causal machine and so on. Here are the answers – no, you can’t turn circuits with negative delays into a time-machine, you can’t go back in time, you can’t even increase frequency of a chip. So calm your nerves and allow us to debunk myths behind negative delays. In this article- we’ll define delays, explain negative delays and sources thereof.


What is propagation delay?


Signal propagation delay is, nothing, but measurement of time between two signal. These two signals could be anywhere in the circuit, i.e. input and output pins of a cell, two nodes of an RC tree or start and end point of a time path.


In the context of a cell or circuit, change in input pins state could cause a change in output pin. Signal is said to have reached a point of no return in the transition, once it crosses a certain threshold. These thresholds are predetermined for the circuit. They could be different for rise and fall transition, input and output pin of a circuit or standard cell. These are typically set at 50 percent of the rail voltage (difference between power and ground voltages) of a signal. In this context rise or fall (propagation) delay of a circuit/cell is defined as


propagation delay = 50% threshold of output transition – 50% threshold of input transition


Under normal circumstances, propagation delay of a circuit/cell is positive, i.e. input signal reaches its 50% threshold before output signal reaches its 50% threshold.


But, how can delay go negative?

Sometimes cell (typically with strong drive strength) may exhibit negative propagation delay. This does not mean that standard cell’s input and output have non-causal relationship. This is simply a manifestation of choice of delay threshold points. Picture below shows an example of negative delay of a simple inverter, when falling input A transition causes a rising transition at output Y.

Negative delay of standard cell (inverter circuit)

It is easy to see in the picture that input signal A starts to fall at 0ps, whereas output signal does not move from low voltage (ground, VSS or 0.0V) until 235ps. This reinforces our earlier statement about causality of these two transition. Given rail voltage of 1.2 volt, delay threshold point of 50% translates in to a 0.6V of theshold. Notice that input reaches 0.6 Volt (50 percent threshold of input rail voltage) at 500ps, whereas output is able to reach this threshold 0.6 Volt (50 percent threshold of output rail voltage) at 467ps.


Using propation delay equation defined above,

propagation delay = 467ps – 500ps = -33ps

And there, we witness negative delay for this transition.



So, what causes negative delays?


There could be many reasons for negative propagation delay of a circuit/cell, some of them are given below.

  • Poorly designed circuits,
  • Poor choice of delay thresholds,
  • Cell/circuit operating beyond their designed specifications,
  • Cell/circuit’s asymmetric PMOS/NMOS drive strength operating under slow input transition time and used to drive small load.




In this article, we defined propagation delay. We, also, saw how a propagation delay could be negative and why does it not represent non-causal relationship between input and output. In the end, we outlined few probable causes of negative delays.



This a guest post by Paripath, find more information here:

Faraday Unveils 28HPC USB 3.1 PHY and 40LP Type-C PHY with PD Controller

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that the availability of its USB 3.1 PHY on UMC 28HPC process, as well as the silicon-verified USB 3.1 Type-C PHY with USB-PD 2.0 support on UMC 40LP process. Faraday introduced the industry’s first USB 3.0 PHY IP solution in 2009; today’s launched USB 3.1 Gen 1 solutions are then designed with optimized PPA (Power/Performance/Area) to address the low-power requirements for mobile devices, digital cameras, MFPs (multi-function printer), automotive, and IoT applications.


Faraday offers a series of USB IP solutions in a broad range of nodes from 0.25um to 28nm, and its related ICs have already shipped over hundreds of millions units. To meet the growing demand for USB Type-C interface, Faraday also delivers USB Power Delivery (PD) 2.0 IP supplying power up to 100W. In addition, Faraday supports its customers with expert ASIC design services and a comprehensive IP portfolio to facilitate the reduction of design risk and cost, enabling quick penetration into their target markets.


“Faraday pioneered composite USB solutions with outstanding mixed-signal circuit design ability,” said Flash Lin, Chief Operating Officer at Faraday. ”The latest Faraday USB 3.1 IP solutions demonstrate our commitment to providing low-power interface IPs for mainstream applications. Based on our deep knowledge of USB IP development and compatibility testing, we are confident we can help customers enhance the user experience of USB products built with our tailored ASIC solution.”


Press Contact
Evan Ke
886.3.5787888 ext. 8689


Sales Contact
Find Faraday’s oversea office