Monthly Archives: September 2017

TSMC to Build 3nm Fab in Taiwan

Taiwan-based semiconductor foundry TSMC announced it will build its cutting-edge semiconductor fabrication plant in Tainan, ending speculation that it might skip Taiwan and invest in the U.S.


“Following careful evaluation, the Company’s planned advanced 3nm fab will be located in the Tainan Science Park to fully leverage the company’s existing cluster advantage and the benefit of a comprehensive supply chain,” the company said in a statement released Friday.


The announcement came ahead of schedule, ending worries that TSMC, one of Taiwan’s biggest firms and employers, might establish the fab in the U.S. due to the potential gap in Taiwan’s water and power supply.


“TSMC recognizes and is grateful for the government’s clear commitment to resolve any issues, including land, water, electricity and environmental protection,” the statement said.




SIDE-CHANNEL ATTACKS: How Differential Power Analysis (DPA) and Simple Power Analysis (SPA) Works

There are many techniques available for hackers to gain access to a system and obtain secret keys or other proprietary information– from invasive methods, such as microprobing, to non-invasive methods, such as cryptoanalysis. However, one of the easiest and most effective ways to extract the contents of a chip is through a side-channel attack using power analysis.


Power analysis is a low-cost and effective way to extract the contents of a chip or smartcard without physically de-processing the part. With power analysis, the variation in power consumption of a device is used to determine the contents of the device. There are two types of power analysis: differential power analysis (DPA) and simple power analysis (SPA).



Simple power analysis is a method of side-channel attack that examines a chip’s current consumption over a period of time.  Since different operations will exhibit different power profiles, one can determine what type of function is being performed at a given time. For example, one can distinguish a multiplication function from an addition function, since multiplication consumes more current than addition. Also, when reading data from a memory, the ratio of 1’s vs. 0’s will be reflected in the power profile.


Kilopass Image 1

Figure 1: Simplified diagram of SPA


With a standard oscilloscope, one can capture the resulting current signature and from it deduce the type of operation. Shown below is an SPA trace showing an entire Data Encryption Standard (DES) operation.

Kilopass Image 2

Figure 2: SPA trace showing a DES operation.
(From: Intro to Differential Power Analysis1)


Or in an RSA decryption key, one can decipher the key based on the fact that each ‘1’ bit appears as a taller bump, while a ‘0’ bit appears as a shorter bump.


Kilopass Image 3

Figure 3: SPA leaks from an RSA implementation.
(From: Intro to Differential Power Analysis1)


SPA is useful when data-dependent features in the power traces are apparent. It may not be practical if there is significant noise in the system. In which case, DPA would be more advantageous.




Differential power analysis is a statistical method for analyzing power consumption to identify data-dependent correlations. This approach takes multiple traces of two sets of data, then computes the difference of the average of these traces. If the difference is close to zero, then the two sets are not correlated. If the sets are correlated, then the difference will be a non-zero number. Given enough traces, even tiny correlations can be seen, regardless of how much noise is in the system, since the noise will effectively cancel out during the averaging.


Here is a typical DPA result showing the average of two sets of traces (A and B) on the first two lines. The difference of these two sets is shown on the third line. The fourth line shows the same trace magnified by a factor of 15. This shows that there is statistical correlation between the two sets. If there was no correlation, the difference would be zero, or close to zero.


Kilopass Image 4

Figure 4: Typical DPA result. This example shows correlation.
(From: Intro to Differential Power Analysis1)


To see how this can be used, take for example, the Advanced Encryption Standard (AES). This encryption algorithm displaced DES and has been adopted by the U.S. government, and worldwide, as the standard for securing Top Secret information. The equation for the encrypted data is given by:


Kilopass Formula 1
Kilopass Image 5


Where S is a look-up table and ⊕ is the XOR of a known input Xn and the encryption key Kn.  To determine the value for Kn, we make several guesses for the value of Kn. The first set of traces falls into the set where the LSB of the output is ‘0’; the second set of traces falls into the set where the LSB of the output is ‘1’. The difference of the average of the two sets is then examined.  Here, we have a trace showing the results of five different Kn values, where the correct key corresponds to the third trace.


Kilopass Image 6

Figure 5: DPA result for different key values.
(From: Intro to Differential Power Analysis1)


Normally, the encryption key is a 128-bit value. In order to test every single value, it would take 2128 attempts, or 3.4028 x 1038, which is pretty much impossible to do.  However, the 128-bit AES key can be broken into 16 bytes, where each byte can be solved individually. Testing each byte requires only 28, or 256 attempts, which means it would only take 16 x 256 or 4,096 attempts to be able to decipher the entire encryption key.




Side-channel attacks, such as DPA and SPA, are dangerous because they allow hackers to circumvent conventional hardware and software security measures. DPA can accomplish in minutes or days what cryptoanalysis and other brute force methods cannot.  Also, since they are non-invasive, they do not leave a trace, allowing for attackers to steal confidential information without being detected. Therefore, measures must be taken to prevent such attacks.


It is relatively simple to prevent SPA. One can inject noise into the system by performing random operations to obscure the real operation. Also, the design should use consistent execution paths and avoid conditional branches.


Preventing DPA is more challenging. There have been numerous published attacks using DPA throughout the years. One method is to decrease the signal to noise ratio– the lower the ratio, the greater the number of traces needed to perform an attack. Temporal noise can be injected into the design by varying clocks, adding random wait states, random data or dummy operations.  An example of this implementation is Kilopass’ Secretcode™ memory. When reading the contents of the memory, random data is injected into the bus so as to obscure the output data.


Another method is to balance the amount of power used for a given data value or operation.  This can be achieved with complementary circuitry or using constant weight code. Balancing the power consumption would reduce the amplitude of the differential trace. Again, the Secretcode memory from Kilopass demonstrates an example of this. The contents of the memory are stored and read in complementary fashion — for each bit, there is a corresponding bit-bar. Therefore, when the contents of the memory are read out, there is always an equal number of 1’s and 0’s.


The most effective and least difficult way to prevent side-channel attacks is to design protocol that will limit the number of transactions that can be performed with a given key, similar to a password timeout. For example, a key can be used only 1,000 times before it is destroyed or replaced with a new key. This would eliminate most attempts at DPA, since DPA requires a statistically significant number of data points in order for it to work.


Power analysis is a powerful tool for side-channel attacks into a system. However, with some forethought and the right countermeasures, one can prevent such attacks.



“Introduction to Differential Power Analysis,”Journal of Cryptographic Engineering, April 2011, Volume 1, Issue 1 Paul Kocher, Joshua Jaffe, Benjamin Jun, Pankaj Rohatgi

“Differential Power Analysis,”Advances in Cryptology – CRYPTO ‘99 Paul Kocher, Joshua Jaffe, and Benjamin Jun

3 “Introduction to Side-Channel Power Analysis,” Colin O’Flynn


This is a guest post by Lee Sun — Kilopass Technology

Sale of MIPS and update on Formal Sale Process

Imagination Technologies Group plc (LSE: IMG, “Imagination”, “the Group”), a leading multimedia, processor and communications technology company, has agreed to sell its worldwide MIPS CPU business (“MIPS”), including all MIPS Intellectual Property (“IP”) and patents, to Tallwood MIPS Inc, a company indirectly owned by Tallwood VC of Palo Alto, CA (“Tallwood”) for a total consideration of $65m in cash.


Tallwood is a Silicon Valley-based venture capital firm with years of experience in the semiconductor industry.


As separately announced today, Imagination has also reached an agreement on the terms of a recommended offer for the Group at 182p per Imagination ordinary share.


The sale of MIPS is on a cash and debt free basis and subject to customary adjustments. $40m of the proceeds are payable in cash at completion and $25m in cash six months after completion.


The sale is conditional on shareholder approval (if required under Rule 21.1 of the Takeover Code) and on the completion of the corporate reorganisation to separate MIPS from the remainder of the Group. Completion of the sale is expected to occur in October 2017.


Following completion of the transaction, cash proceeds will be used to reduce the Group’s debt, with the balance applied for general corporate purposes.


Andrew Heath, Chief Executive of Imagination, said:


“This transaction, which is separate to the offer for Imagination by Canyon Bridge, will ensure MIPS remains an independent licensing business.


“MIPS has gained notable momentum over the last year or so having secured a number of design wins, and made good progress towards profitability.


“This significant progress, allied to Tallwood’s investments in the semiconductor industry, will provide increased customer choice and new job opportunities based on the continued growth of the MIPS business.”


Update on formal sale process


Imagination announced on 22 June 2017 the commencement of a formal sale process under the Takeover Code in respect of the Imagination Group and engaged in discussions with a number of potential purchasers.


Further to the announcement today of the terms of a recommended cash offer for the Imagination Group and the disposal of MIPS referred to above, the formal sale process under the Takeover Code in respect of the Imagination Group and the sale processes for MIPS and Ensigma businesses have now been concluded. One party has not confirmed whether its interest in the Imagination Group has terminated and accordingly it remains a potential offeror for Imagination for the purposes of the Takeover Code.


Accordingly for so long as this party remains a potential offeror, the Company is required to seek shareholder approval for the sale of MIPS at a General Meeting for the purposes of Rule 21.1 of the Takeover Code. A circular is expected to be posted to Imagination shareholders shortly.



Imagination Technologies Group plc  Tel: 01923 260 511


Andrew Heath, Chief Executive Officer
Guy Millward, Chief Financial Officer


Instinctif Partners Tel: 020 7457 2020


Adrian Duffield
Kay Larsen
Chantal Woolcock

Rothschild (Financial Adviser) Tel: 020 7280 5000


Ravi Gupta
Warner Mandel
Yuri Shakhmin


Notes to Editors


About Imagination Technologies

Imagination creates and licenses semiconductor processor IP (intellectual property) for graphics, video and vision processing, general purpose and embedded processing (CPU & MCU). Imagination’s customers use Imagination’s silicon IP to create the Systems on Chips (SoC) that power electronic devices. Imagination has built three strong brands around these processing blocks: PowerVR in graphics and multimedia; MIPS in processors; and Ensigma in connectivity. See:

About MIPS

The MIPS family of CPU IP is composed of a portfolio of low-power, high-performance 32/64-bit processor architectures and cores, which range from high-performance cores for high-end applications processors to smaller cores for microcontrollers.

MIPS cores are produced in three classes of performance and features: Warrior M-class are entry-level ultra low power small cores for embedded and microcontroller applications; Warrior I-Class are scalable mid-range, feature rich cores for mainstream Linux and Android devices; and Warrior P-Class are high-performance cores for demanding applications.

In the year to 30 April 2017, MIPS’s loss before tax was £8.0m and it had gross assets of £11.7m.

About Tallwood

Tallwood is a leading Silicon Valley venture capital firm with a philosophy to invest in differentiated technologies and products that will have a significant impact on the semiconductor industry. Led by Dado Banatao, who is renowned throughout the high technology industry as an innovator, strategic investor, and philanthropist, Tallwood builds close working relationships with its portfolio companies to maximize growth opportunities.

Moortec’s Expansion Continues with New UK Headquarters

Moortec, specialists in embedded in-chip subsystem solutions, are continuing their expansion with a move to a new UK Headquarters.


The new state of the art facility is located in the Plymouth Science Park which is the largest Science & Technology centre in the South West.


“The four-story office and lab complex provides more space for our growing team and will allow us to build on our position as the only dedicated provider of embedded PVT monitoring IP as well as supporting our continued product development and projected growth. We decided to stay within the Science Park due to its excellent facilities and strong on-site science based community”.


“The rapid growth of Moortec in the last two years has meant that we are now operating on a truly global scale with customers in the US, China, Taiwan, South Korea, Japan, Russia and Israel”. said Ramsay Allen, VP of Marketing at Moortec.


Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm.


The PVT monitoring subsystem IP is designed to optimise performance in today’s cutting-edge technologies, solving the problems that come about through scaling of devices. Applications include Datacentre & Enterprise, Automotive, Mobile, IoT, Consumer and Telecommunications.


Last year Moortec secured investment from Altitude Partners, the regional private equity fund. Altitude’s investment has assisted the business in developing and strengthening both its engineering and sales team and adding new silicon proven designs to their IP portfolio.


About Moortec


Established in 2005, Moortec provide in-chip monitors and sensors, such as embedded Process Monitors (P), Voltage Monitors (V) and Temperature Sensors (T). Moortec’s PVT monitoring IP products enhance the performance and reliability of today’s Integrated Circuit (silicon chip) designs. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provide a quick and efficient path to market for customer products and innovations.



For more information please visit


Contact: Ramsay Allen, +44 1752 875133,

Sondrel Expands into India

Sondrel, a UK headquartered IC Design Consultancy, today announced the establishment of an entity in India, having opened its first engineering design centre in Hyderabad. The company provide concept to silicon design services to an international client base.


The continued rapid growth of Sondrel has seen new design centres opening in the UK, Europe, China and Morocco. Establishing an office in India expands the company’s reach into an important region within the semiconductor sector, and brings its international network of design centres to eight in total.


The twenty-five strong engineering team in Hyderabad formerly worked for Imagination Technologies, and specialise in graphics and image processing technologies. The Sondrel office is in the Madhapur district, in Hitech City, a hub for many global semiconductor and technology companies. Sondrel is immediately looking to hire more engineering consultants, and to grow the team.


India is a major player within the global semiconductor sector. According to the India Electronics & Semiconductor Association, the Indian Electronic System Design and Manufacturing (ESDM) market will grow from US$ 76 billion in 2013 to US$ 400 billion by 2020. According to the Department of Electronics and Information Technology (DeitY), nearly 2,000 chips are being designed every year in India and more than 20,000 engineers are working on various aspects of chip design and verification.


Sondrel CEO, Graham Curren explained, ‘This is another milestone for us, opening our first design centre in India, and we look forward to being part of its technology community. We are proud to be a UK headquartered company, with an international outlook. Our engineering teams collaborate and share their expertise across the company, giving us great strength and depth to tackle today’s complex design challenges. The engineering team based in Hyderabad comprise of senior managers and talented design, verification and implementation engineers. They join us with an impressive track record of project experience for complex SoC designs and are a valuable addition to our global engineering team.’


He continued, ‘Sondrel has a reputation within the industry for our expertise in large complex digital designs. Our application focus in India is in Artificial Intelligence (AI) – products that require high computational performance that support solutions for ADAS systems, virtual and augmented reality products, and machine vision and learning devices. The project work that we do is challenging, and I know that the team can meet these challenges. Employees of Sondrel can expect to gain valuable experience working on multiple project engagements, many of which will be on cutting edge process technologies.’

Pure-Play Semiconductor Foundry Growth Is At <40nm Process Nodes

IC Insights has just released its September Update to The McClean Report.  This 32-page Updateincludes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.


In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).


Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.


TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.


Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.


In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.



More Information Contact

For more information regarding this Research Bulletin, please contact Bill McClean, President at IC Insights. Phone: +1-480-348-1133, email: