Monthly Archives: October 2017

OmniPHY to Demonstrate Automotive Design Solutions at IEEE-SA Automotive Ethernet Technology Day

OmniPHY, Inc. OmniPHY Semiconductor, Inc. today announced it will be showcasing how it leverages automotive Ethernet technology to create robust automotive semiconductor IP solutions at the IEEE-SA Automotive Ethernet Technology Day forum. The event is being held on October 31 – November 2, 2017, at the San Jose McEnery Convention Center.


OmniPHY will be showcasing its IP solutions, with an emphasis on Automotive Ethernet IP and Connectivity Solutions.


Automotive Ethernet is a new standard that will be the backbone of the in-car network powering vehicles to become autonomous ‘Servers with Wheels.’ The first designs support 100 Mb communications over a single pair of unshielded twisted pair. Come see a live demonstration of this exciting new technology. Additionally, OmniPHY will be discussing its brand new Automotive Switch technology. Engineers will be on hand to describe how we create IP for the automotive market.


OmniPHY’s complete line-up of Automotive Ethernet IP comprosies:

  • 100Base-T1 PHY IP
  • 1000Base-T1 PHY IP
  • Automotive Switch IP
  • Time-Sensitive Networking Controller IP
  • Automotive-grade SGMII Interface IP


In addition, experts from our design and applications teams will be on hand to answer questions and engage in technical dialog.


The event is being held on October 31 – November 2, 2017.


The San Jose McEnery Convention Center, Booth #21


About the IEEE-SA Automotive Ethernet Technology Day:

This conference and its exhibition are the premier venue for OEMs, suppliers, semiconductor vendors and tool providers to discuss and learn about the evolution of Ethernet standards, technologies and applications in the automotive environment
About OmniPHY:

OmniPHY is a leading provider of highly specialized interface IP and communication technology, offering customers greater design margins and fast time-to-market for emerging standards, including 1.25-28 GB/s PHY designs and 10/100/1000BASE-T Ethernet in advanced processes. The company serves the Automotive, Industrial, and Enterprise segments through its lineup of silicon-proven PHY IP.


For more info:


See here OmniPHY profile page on AnySilicon:


asicNorth announces immediate availability of its IoT Endpoint ASIC Platform

asicNorth is pleased to announce immediate availability of its silicon proven platform to rapidly deploy IoT Endpoint ASICs – IoTa. Samples are available for prototype development.


IoTa is structured to be highly configurable enabling support for various radio protocols, ARM Cortex®-M0 compatible peripherals, analog/mixed-signal requirements, and external sensors. IoTa will enable customers the benefits of reduced development costs and faster time-to-market than traditional ASIC developments. Customers may quickly customize the design for their needs or use IoTa as is.


IoTa features IP and services from IoT Design EcoSystem partners – Silvaco, Silicon Creations, Faraday Technologies, UMC, and asicNorth. IoTa has the following capabilities:


  • ARM Cortex®-M0 32-bit microcontroller
  • 128 KB on-chip SRAM for program and data storage
  • Several options to interface off chip sensors – SPI, I2C, UART, and 16 general purpose IO
  • Three (3) 16-bit timers
  • JTAG debugging interface
  • Watchdog Timer
  • Wakeup Interrupt Controller
  • 12-bit DAC
  • 12-bit, 4 channel ADC
  • Fast start, ultra-low power IoT PLL
  • 1.8V crystal oscillator I/O cell


Initially targeting Smart City LPWAN applications, IoTa supports multiple radio standards through innovative system-in-package design. The integrated high precision analog / mixed-signal cores provide control and measurement for many sensor applications including I-to-V, C-to-V, L-to-V, and small signal sensing. By starting with proven silicon, asicNorth’s customers will be able to prototype their system and develop firmware immediately while ASIC customization proceeds in parallel, which will greatly accelerate their customer’s time-to-market.


“IoTa will provide the next level of service to IoT Design EcoSystem customers,” comments Mike Slattery, asicNorth President. “With a hardware architecture proven in silicon, customers will be able to start prototype development, including firmware, immediately, significantly accelerating time-to-market.”


“This is a great example of the synergy created by the IoT Design EcoSystem,” says Warren Savage, General Manager of Silvaco’s IP division. “Our proven IP subsystems allow customers to quickly create fully functional products. We are quite pleased to partner with ASIC North and be a part of the launch of their innovative IoTa platform.”


About ASIC North:
ASIC North, Inc. was founded in January 2000 with one purpose in mind; to deliver the highest quality design services possible. In an industry that can be quite volatile at times, it is important to have a design partner that you can depend upon to deliver the VLSI designs you need when you need them. Today, asicNorth is enabling high-tech industry leaders and startups alike with a variety of design services in digital, analog, mixed-signal, and RF design. These capabilities, along with our focus on IP Design, Circuit Characterization; Supply Chain Management; and Turnkey Products allow us to support the needs of our clients at any point in the IC product development cycle. asicNorth is “Bringing Analog / Mixed-Signal to ASIC Design”. asicNorth is a LoRa Alliance member. To learn more about asicNorth, visit us at


About Faraday Technology:

Faraday Technology Corporation is a leading fabless ASIC / SoC and silicon IP (intellectual property) provider, ranking in top 50 fabless IC suppliers in the world and top 10 in Taiwan. Headquartered in Hsinchu Science Park, Taiwan, Faraday has services and technical support offices around the world, including in US, Japan, Europe and China. Since established in 1993, Faraday has been acknowledged its expertise and capabilities with over thousands of successful designs in a wide range of application, covering consumer electronics, multimedia, display, communication, networking, and PC peripheral/storage, along with hundreds of million ASIC chips shipped annually worldwide. Faraday is one of the few leading ASIC / SoC vendors with a comprehensive self-developed IP portfolio. Accumulating thousands of valuable IPs, Faraday’s IPs are mostly silicon-proven, and includes cell library, memory compiler, processor cores, analog IP, peripheral IP, and complete interface IP solutions. These IPs help to greatly lower customers’ integration risk, IP licensing costs, and shorten the time-to-market. To learn more about Faraday Technology, visit us at


About Silicon Creations:

Silicon Creations provides world class silicon IP for precision and general purpose timing (PLLs), SerDes and high-speed differential IOs. We have a deep commitment to our customer’s success and to providing complete support. Our careful development procedures and strong QA result in robust and correct designs. And in our labs we comprehensively test all key blocks. As a result our IP has an excellent record of first silicon to mass production in over 300 chips for over 100 customers. Our IP is used in diverse applications including mobile phones, consumer devices, processors, network devices and medical devices and in technologies from 180nm to 7nm, and has earned “best-of” awards from TSMC and SMIC.

Silicon Creations was founded in 2006, is self-funded and is growing. We have development centers in Atlanta, USA and Krakow, Poland and world-wide sales representation. To learn more about Silicon Creations, visit us at


About Silvaco, Inc.:

Silvaco, Inc. is a leading EDA and IP provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Silvaco delivers a full TCAD-to-sign-off flow for vertical markets including: displays, power electronics, optical devices, radiation and soft error reliability and advanced CMOS process and IP development. For over 30 years, Silvaco has enabled its customers to bring superior products to market with reduced cost and in the shortest time. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.


About UMC:

UMC is a leading global semiconductor foundry that provides advanced technology and manufacturing for applications spanning every major sector of the IC industry. UMC’s robust foundry solutions allow chip designers to leverage the company’s leading-edge processes, which include 28nm poly-SiON and gate-last High-K/Metal Gate technology, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i. Fab 12A consists of Phases 1-4 which are in production for customer products down to 28nm. Construction has been completed for Phases 5&6, with future plans for Phases 7&8. The company employs over 17,000 people worldwide and has offices in Taiwan, Japan, Korea, China, Singapore, Europe, and the United States. To learn more about UMC, visit us at

Understanding ASIC Development

ASIC is an acronym for Application Specific Integrated Circuit. It is designed for a specific or customized use as opposed to one that serves a generally available. Examples of ASIC include chips that are designed to run specific devices such as Apple A11 CPU for example. You can find ASIC chips as part of any product that requires specific features that cannot be achieved by off-the-shelf-ICs. The main reason for using an ASIC is to gain add specific features to your product or (and) gain competitive edge. For that reason many companies are using customized chips for their products.


Thanks to advancing technology, ASIC development has managed to grow from roughly 5,000 gates to over 100 million which means that its use has grown exponentially as well. However, the ASIC has been replaced in some ways by the FPGA, the Field Programmable Gate Arrays that allow for chips to be programmed instead of designed from scratch. The FPGA is found in many different applications, but the ASIC is still quite popular in large devices and designs. However, it is true that ASIC designs can become quite expensive in development cost depending on their use.


ASIC Development


The early ASIC designs that were introduced into personal computers in the early 1980s used what was known as gate array technology. The ASIC was initially considered an economic means of handling computer graphic programs and displays. However, as the ASIC was developed its potential was seen for other devices and uses thanks to the gate arrays that could customized for each chip. A base pattern was developed for ASIC which allowed it to be manufactured cheaper and then be customized for specific uses.


By the mid-1980s, the limitations of the ASIC were becoming apparent in the manufacturing process with many designers having to use specific tools to complete the design which drove up the costs. The creation of standard cells helped to improve gate density and provide for excellent performance while cutting down the cost of manufacturing the ASIC.


The development of standard cell design in the 1980s was augmented a decade later when tools for logic synthesis became available. This allowed for HDL descriptions to be included for gate level netlists. The result was that integrated circuits that used the standard cell design could be further manipulated to expand their function.


computer cpu or central processor unit chip on mainboard.Technology background with computer processors CPU concept and blue circuit, board texture.



Different Types of ASIC Development


There are three basic types of design used for the ASIC:


  • Gate Array
  • Full Custom
  • Structured


The gate array design uses transistors and other devices in diffuse layers which are predefined and unconnected before the metallization process. From two to nine layers may be placed on the ASIC when using this design. The full custom version differs thanks to the reduced space, improved performance, and its ability to integrate with analog components along with microprocessor cores that create a system on the chip.


The structured design is the latest ASIC development and is still new in the industry, although there are still strong similarities to the other designs. What makes it different is that this design is quicker to produce and it bridges the gap between standard ASIC designs and the gate arrays that are field programmable.


The ASIC continues to develop even though advancing technology has changed somewhat since its inception in the early 1980s.


Get instant price quote for your ASIC Development project: Click Here

M31 Technology and Corigine have launched the world’s first USB-IF certified 28nm Superspeed+ USB 3.1 Gen 2 IP Solution

M31 Technology Corporation, a global Silicon Intellectual Property (IP) boutique, today announced that Corigine’s USB 3.1 Gen 2 PC host and device controller intellectual property (IP) with M31 28nm PHY is certified by the USB Implementers Forum (USB-IF) and compliant with USB SuperSpeed+, the fastest USB speed standard.


USB SuperSpeed+, also known as USB 3.1 Gen 2, doubles the uppermost USB transfer speed to 10 gigabits per second. “At this speed, it is possible to take advantage of the performance of the latest generation of SSD drives and unleash smartphone and video applications that depend on high-speed data transfers,” remarks Mike Demler, senior analyst at The Linley Group. With this USB-IF certification, Corigine’s IP will enable deployment of millions of devices that need the fastest USB speed.


“M31 is pleased to offer the 3.1 Gen 2 PHY in various process nodes including 28nm, 12nm and 7nm,” adds Scott Chang, M31’s vice president. “M31 is delighted to have USB-IF certification along with Corigine’s USB Gen 2 controllers and pleased to offer the 3.1 Gen 2 PHY in 28nm as part of Corigine’s complete and highly competitive offering.”


“Corigine’s comprehensive USB-IF certified IP solution offers a differentiated memory-efficient, power- and cost-sensitive architecture at the fastest USB speed,” says Sheng Lu, president of Corigine. “This certification creates a highly competitive alternative to what’s currently available for designers to incorporate the highest-performance USB functionality, providing them with greater product design flexibility.”


Corigine used its USB 3.1 Gen 1 IP experience to deliver a compact USB 3.1 Gen 2 IP core with a reduced power, memory-efficient and configurable design. A complete development environment from Corigine includes the PC host and device controllers, verification IP, IP subsystems, IP prototyping and software development kits, enabling shorter design cycles for customers.


M31 Technology USB 3.1 PHY IP is extremely popular and well received by their existing customers for maturity, quality, compact size and support ranging from most popular to most advanced nodes. M31 Technology believes in first time silicon success and offers complete and high quality solutions to their customers.


Media contact: Shirley Hsu +886 3 5601866 ext. 123



M31 Technology Corporation is a professional silicon intellectual property (IP) provider. The company was founded in July, 2011 with its headquarters in Hsinchu, Taiwan. M31’s strength is in R&D and customer service. With substantial experiences in IP development, IC design and electronic design automation fields, M31 focuses on providing high-speed interface IP, memory compilers and standard cell library solutions. For more information please visit


ABOUT Corigine

Corigine, Inc. is a fabless semiconductor and IP company headquartered in Santa Clara, Calif., with design centers in Hong Kong, Nanjing and Shanghai, China. Corigine delivers intellectual property (IP) solutions for high-speed I/O as well as semiconductor products for connectivity, storage and machine learning applications targeted at cloud, automotive and smart city markets. Corigine’s seasoned IP experts from top fabless semiconductor companies leverage an advanced architecture to deliver innovations for emerging applications for reduced power, area and memory utilization while ensuring maximum performance and configurability.

Montage Technology Licenses Allegro DVT’s IP for Next Generation Set-Top Box Chips

Allegro DVT, a leader in video compliance streams and video codec semiconductor IP solutions, announced today that Montage Technology, a leading fabless semiconductor provider for smart home entertainment and data center markets, has licensed Allegro DVT’s AL-E100 multi-format H.264/AVC and H.265/HEVC encoder IP for integration into its next-generation set-top box (STB) products.



Montage Technology provides highly integrated and customizable STB system-on-chip (SoC) solutions for smart home entertainment. By integrating Allegro DVT’s AL-E100 encoder IP, Montage is enabling new use cases such as high-quality streaming of television programs to secondary displays at home.


“Allegro DVT’s AL-E100 encoder IP offers excellent video quality. That perfectly meets our requirements for STB transcoding and streaming applications. The encoding quality combined with extremely small silicon area and low power consumption allows us to offer this new, innovative feature to broader markets.” says Mr. Gene Liu, General Manager of Montage LZ Co. LTD.


Pierre Marty, CEO of Allegro DVT, comments: “We are very proud to have been selected by Montage Technology, a company that is rapidly gaining market share in the global STB SoC market. Our AL-E100 encoder IP proves to be a perfect solution for consumer applications by offering the smallest silicon area thanks to the true multi-format architecture while maintaining best-in-class video quality.”


Allegro DVT’s AL-E100 IP is a configurable multi-format encoder supporting H.264/AVC, H.265/HEVC, VP9 and JPEG formats. It is scalable up to 4K and 8K resolutions. It can also support unique end-to-end sub-frame latency required in many applications such as ADAS, virtual reality and drones.


To learn more about Allegro DVT’s video codec semiconductor IP solutions, visit


About Montage Technology

Montage Technology is a leading fabless semiconductor provider focusing on the data center and smart home entertainment markets. In the smart home entertainment market, Montage provides highly integrated and customizable OTT/STB total solutions for home entertainment, and offers feature-rich, cost-effective consumer IoT solutions for wireless connectivity everywhere at home. Montage’s sophisticated technology platform allows it to deliver integrated solutions that meet the expanding needs of customers through continuous innovation, efficient design and rapid product development.


About Allegro DVT

Allegro DVT is a leading provider of H.264/MPEG-4 AVC|SVC|MVC, H.265/HEVC, AVS2, VP9 and AV1 solutions, including industry standard compliance test suites, H.264/AVC, H.265/HEVC and VP9 encoder, codec and decoder hardware (RTL) IPs.


Contact: Tel: +33-4764-26685, email:



Guide to Semiconductor Wafer Sort

Wafer sort (or wafer test), is a part of the testing process performed on silicon wafers. Wafer sort is a simple electrical test, that is performed on a silicon die while it’s in a wafer form.


Wafer sort’s main purpose is to identify the non-functional dies and thereby avoiding assembly of those dies into packages. In many cases, wafer sort is a simple and quick test that focuses on a few electrical parameters that are most likely to fail.


Wafer testing is performed during IC production on every wafer and every silicon die. Otherwise, there could be defective semiconductor dies that will go through the assembly process and therefore lead to unnecessary expenses at the end of the manufacturing process.


Photo: Probe Card (credit: Synergie-CAD)


One can imaging wafer sort as a financial decision that depends on yield, volume and packaging cost. But in some cases, companies perform wafer sort to monitor the silicon foundry yield. This feedback is then feedbacked to the fab to further optimize the silicon manufacturing process and hence improve the process yield.


A digital wafer map is attached to each wafer that has been tested to label the passing and non-passing dies.




How the Wafer Sort Works?

Called by different names such as the Electronic Die Sort (EDS), Circuit Probe (CP), and the Wafer Test (WT), This is the testing performed on the wafer or part of the semiconductor that carries the internal circuitry. Because the circuitry is so small, visual detection of any defects is virtually impossible. So, the testing itself is performed using specific equipment after the wafer has been created.

The wafer testing is done just before it is sent to the die packaging phase. The integrated circuits that are found on the wafer are checked for defects. The process uses test patterns to find any defects and thus eliminate the wafer from the next step in the process. The testing itself is performed by an ATE that has a wafer prober.


What is a Wafer Prober?

This is the device or machine that carries out the functions of the wafer sort or testing of the integrated circuits. How it works is rather simple. During the testing process the probe card which consists of several contacts that are microscopic in nature are located inside the wafer prober when the wafer itself is positioned for electrical contact. The wafer is mounted on what is known as a wafer chunk to keep it in position. The hold is vacuum-sealed which means that it is strong, but temporary so that another wafer can quickly be moved into position once the testing is over.


When each die has been tested electronically by the prober, it moves to the next die where another line can be tested. The prober will load and unload the wafer from the carrying device. Plus, it is equipped with optics for automatic pattern recognition so that the wafer is aligned properly for the testing process. That way the testing can be performed with the utmost accuracy and it ensures that a failure of any test is not due to the wafer being incorrectly aligned.


The contact pads on the wafer are touched by the tips of the needles from the wafer prober. This allows electricity to be properly conducted through the wafer which if successful completes the test so that the next line or circuit can be tested. However, if the electrical test does not pass through, the wafer is then moved from the manufacturing process for separate testing to ensure that it is defective.


The wafer prober can also handle multi-die packages like the System in Package (SiP) or the Stacked Chip-Scale Package (SCSP) thanks to the use of non-contact probes. This allows for the proper identification of the Known Tested Die (KTD) as well as the Known Good Die (KGD) which are vital to increasing the yield of the overall system.


Additional Testing

The ATE will also test circuitry along the scribe lines. Performance of the device can be rated when using line test structures. There are companies that get a good amount of information by using this process. There are some dies that include internal spare resources that are used for repairs such as found on flash memory IC. If some test patterns are not passed, the additional resources available can be used.


If there is no redundancy of the die that has failed in certain tests, then it will be discarded as useless. During the testing process, circuits that do not pass electricity are marked with a small ink dot located in the middle or the wafermap will store the information of failed or inactive circuits.


What is a Wafermap?

This is a map that reveals the dies that are passing and non-passing using bins. The bin itself will be defined as either good or bad die. The wafermap will then be sent electronically to the assembly house which only picks up passing dies by choosing the bin number that contains good dies.

In the past, the good dies were marked by ink dot, but this process is not common anymore. The use of ink dots allows for visual inspection as the operator can now disqualify a die based on the ink dot. While only dies that pass all the test patterns are used, there are cases in which one that did not pass all the test patterns can be incorporated if their flaws do not significantly interfere with the device where it will be placed.


After IC Packaging

The packaged chip will be tested another time during what is known as the IC phase. This testing process is very similar, if not actually the same as the original wafer test approach. While this might be seen by some as redundant, it does serve as an extra step that can catch a defects in the assembly process, for example, missing bumps or wirebonds.

This double-check helps keep defective dies from being sold or used in devices which creates considerable cost in detecting and replacing. However, there is considerable cost in the testing process, so it is not surprising that some companies that are producing a high yield of dies will skip testing altogether and risk blind assembly for greater efficiency.


Find here a list of IC testing companies.