Monthly Archives: December 2017

Arastu Systems enhances outreach with the establishment of its Global Sales Channel

Arastu Systems, a product engineering services company, based out of California, has today announced the active presence of its Global Sales Channel spanning across multiple countries. The company has partnered with established companies Avant Technology, Inc. and NRG Technologies, who would be representing Arastu Systems IP products in Asia and Israel semiconductor markets respectively.


In retrospect, Arastu Systems team of sales experts observed significant traction from multiple countries other than India and USA where they have their Design House and Headquarters respectively. Upon thorough research and insight generated through Marketing efforts, Arastu Systems sees the value it can bring to the SoC companies and the entire Semiconductor ecosystems by having multiple shadow’s managing the region-specific Sales efforts.


Avant Technology, Inc. is an established player in the semiconductor industry and have been actively contributing for the Asian markets for more than two decades now. On the other hand, NRG Technologies is focused at the Israel region only and is assisting many Israel based Fabless Semiconductor companies and System Houses. This enhanced sales presence will also assist Arastu Systems to market their newly established set of products and services in the IoT segment.


“Arastu Systems welcomes the existing opportunities generated from the newer market horizons” says Umesh Patel, CEO, Arastu Systems. “Customers are already leveraging the sales channel, which has made the communication process much simpler and flexible”.



About Arastu Systems, Inc.

Arastu Systems is contributing in the Semiconductor Industry by providing high quality and value added product engineering services through silicon and software engineering. The company provides complete Front-end Digital Solution, Robust and Flexible products in Memory and Networking area. Additionally, they are also catering to demand generated in the IoT segment by leveraging their IoT related products and services. Arastu Systems understands the customer’s pain points and therefore believe in forging relationship by providing customized solutions. They are headquartered at San Jose, California and have a design center in Ahmedabad, India. For more information please visit,


Media Contact:

Harsh Parikh, Manager, Marketing


Creonic Launches 5G Product Line with Polar and LDPC FEC IP Cores

Creonic GmbH today announced its new product line for 5G FEC (forward error correction). The product line covers LDPC decoder as well as Polar encoder and decoder IP cores for this latest 3GPP specification (3GPP Release 15).


The LDPC core comprises HARQ combining, rate matching, LDPC decoding, and CRC check. It supports base graph 1 and base graph 2 type LDPC codes with all code rates. The Polar decoder is designed for lowest latency requirements.


The new IP cores are suitable for ASIC and FPGA technology. They are updated as the 5G specification evolves and will be ready when the 3GPP specification is finalized.


As leader in FEC IP cores, Creonic is proud to offer the new 5G IP cores following the continuous develepment effort of its silicon-proven product portfolio.


For more information, please visit the product pages or contact us.


About Creonic

Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The company offers the richest product portfolio in this field, covering standards like DVB-S2X, 5G, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit our website at

HDL Design House Launches New Website


Belgrade, Serbia – December 19th, 2017 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, announced today the launch of its new website. The newly redesigned website offers quick and easy access to essential information and features, offering a more comprehensive understanding of the company’s products and services. The website also has a resource section containing technical articles and webinar recordings, along with updated company news and events, products and services overview, and an updated online job application form.


Visitors can benefit from clean and modernized design, improved functionality and enhanced content, with newsletter subscription option. The new website has been designed to provide user-friendly experience with improved navigation and functionality throughout, allowing customers to access detailed product and service information, with the option to share information across all major social networking sites. Developed using the latest technology, the site is compatible with today’s browsers and mobile devices. The new website goes live today, December 19th, 2017 and is located at the same address:


“We are excited about our new website launch and the new benefits it provides for customers, partners and media to better understand HDL Design House’s diverse and extensive expertise,” said Predrag Markovic, HDL Design House CEO.  “We believe that this new site will allow our visitors to have a very informative experience as we continue to grow and expand our offer for various market applications.”


HDL Design House’s new website will be updated on a regular basis with news, events, business activity, and various technical information. Visitors are encouraged to explore the website and sign up for company’s newsletter at



About HDL Design House:


HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 160 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). HDL DH joined the ARM® Approved Design Partner program, through which leading SoC design houses are recognized by ARM as accredited partners in specific technologies and activities. For more information, please visit


The True Cost of IC Test

The other day I was having lunch with a friend I had not seen in some time who had recently come back from a ten-day trip overseas. This was his sixth such trip in the past twelve months made to check on production test activities at the OSAT his company had picked to run their production test.


My friend looked tired and I asked him why he had to make so many trips to manage what should have been a pretty smooth activity. He explained what so many of our customers have told me over the years: “things don’t always work out as planned.”


Cost of test has long been a significant factor in the production cycle of ICs.  The goal is to have adequate test coverage in test so as to not ship problematic units to customers, but also to minimize test times and their associated costs.   There has long been the belief that the quicker you can get your product production test needs shifted to low-cost factories (often in locals such as southeast Asia), the lower cost you will incur—and as a result, there has been an imperative to do so.


But does this plan always lower overall cost? And is it the best plan for everyone?


I won’t argue that in large volumes even fractions of pennies make a huge difference to the bottom line. But is that where your company is today?  Over time, it may certainly make sense to take mature, stable, simple production activity in high volumes to factories that are set up to process exactly that, but there are numerous reasons, as my friend can validate, that keep products from getting there and why he needed to make six trips to “check” on things.


#1: Complex Test Flow

Large-scale IC production test is a factory; factories work well with predictable, organized flows. Needing to step outside of that is painful and that pain often translates into errors, and inability to execute or price increases/adders to pay for the customization and delays.


#2: Engineering Changes

If you think releasing a test program to production is a onetime event for a given product, guess again.  Test program changes do get made, and often engineers need to step in and validate, alongside their production partner, what effect those changes have. Again, change is not a friend of the high-volume factory and a place where problems and cost can be introduced. Further complication is brought about when language and/or geographic constant come into play.  Engineering iterations can really slow down and mistakes can be made.  Some of the trips my friend made were out of frustration of not being able to interact effectively remotely.  Also consider that the trips themselves are expensive–and while that expense does not hit the gross margin of the product, it certainly does hit the bottom line of your company and takes a toll on the constrained engineering resources.


#3: Low Volumes

Perhaps I should have said lower-than-expected volumes.  Of course, we all aim for success and for many that means hockey stick forecasts, with production volumes soaring.  That’s a great plan; and when you reach the hockey stick and the volumes are there, go get the benefit of high-volume cost reductions. But until you are, there is often little to no cost savings on lower volumes. And given fixed costs and some of the other inflexibilities of the high-volume factories, consider slowing down your rush to move product there.


When my friend and I examined the test flow they were employing, the differing flows for each of the few customers they had and the volumes of units against the all-in pricing he was getting, it turned out I could have offered him very competitive pricing to test the units on our test floor in the Silicon Valley (not an area known to be low-cost).   Intuitively this doesn’t make sense, but when you look more closely, the fact is that EAG’s test floor is geared to NPI (New Production Introduction) efforts, which means we have a flexible engineering focus and in the early days of production ramp supporting dynamic changes and complexities can cut time and effort to quickly arrive at solutions and continue to support them in production. Flexibility is not only a feature of our business, but an essential part of it. This means that while we have robust processes, we can adapt to serve customers’ needs without customers bending to fit the needs of our ‘factory.’


So, as you consider your production test plans, I ask you to take a pause and give some serious thought to what your needs really are.  Ask yourself what the true costs are.  Of course, there is the test cost, but make sure you consider the cost of time delay, the cost of troubleshooting and debugging, and decide what wear and tear and other headaches cost your team your organization in dollars… and please reach out to EAG if you think we can help.


On the other hand, if you really enjoy long plane rides, traveling last minute over the holidays to deal with production issues at quarter end, or managing through similar unanticipated adventures, you can talk to my friend…. I think they are hiring.



This is a guest post by: Aram Sarkissian, General Manager at EAG Laboratories

The Impact On IC Silicon Area When Using A Custom Design Grid

Using a custom design grid in an IC layout offers many important advantages, but there is a potential price to pay in using them, particularly in terms of increased IC area. In this article we analyse the actual cost implications in detail.


Key advantages of a IC Layout Design Grid:


  • Improved uniformity across a design (conductor spacing, width & density)
  • Reduced lateral capacitive coupling
  • Better control of density requirements
  • Design rule clean by construction
  • Enhanced design for manufacturability
  • Reduced layout time (less requirements to zoom in/out, use of rulers, no need to be concerned about DRC fixes)
  • Easier to migrate layout from one technology to another (between foundries and/or between nodes)


Overall, grids make the layout process faster, more uniform and guarantee a DFM clean layout by construction. However, whilst these advantages are likely to reduce both development costs of and cost of final silicon, engineers should also be aware that there are also some disadvantages to using custom grids.


Key disadvantages of a IC Layout Design Grid:


  • Placing devices on design grid can be time consuming (automation can help)
  • Schematic designs which are not optimised for a custom design grid, can potentially be slower to layout
  • Potential increase in silicon area!


By far, the largest concern about implementing a gridded design, is the potential area cost due to using non-minimum metal, OD and poly spacing in the layout.


There are two places where conductor spacing can impact silicon area – device spacing (particularly when devices are placed as arrays) and routing channels. Here we will analyse the area cost of using a design grid in both occurrences. 


Cost analysis – device arrays



The boundaries above represent the device/cell area, plus half minimum conductor spacing on all sides, such that when the devices are placed down with abutting boundaries, device spacing is adhered to. By snapping a device (or cell) to a design grid, you increase the placement boundary area, effectively increasing the device area.



When the devices are placed as an array, we can analyse the area of both the minimum rule boundary and the gridded boundary:


Minimum Rule                                                                    Design Grid



From this we can now determine the factor by which the area has increased:



So the overall increase in area is:

Area Increase=    


Some very important points are worth observing from this analysis:

  • The larger x is with respect to Δx and/or y is with respect to Δy, then the smaller the area increase will be. So the larger the device size, the smaller the impact will be on silicon area when using design grid.
  • If device sizes can be chosen such that y and x are already on (or close to) a design pitch, such that Δx and Δy are zero (or small), then the smaller the impact will be on silicon area.


Practical Example:


If we take a practical example of a minimum length MOS device on a generic 28nm technology.


• Poly to poly spacing (100nm in this case) is the dominant spacing.

• The boundary width extends for 50nm on either side of the dummy poly stripes, meaning there will be the minimum 100nm horizontal spacing between stripes of adjacent cells.

• The boundary width is 390nm

• The height of the poly stripes is 580nm

• Allowing for poly to poly vertical spacing of 100nm between cells, the boundary height is 680nm.

• Device boundary is x=390nm y=680nm

• Total device area =265,200nm²




The device, when arrayed up, will adhere to minimum poly to poly spacing on all sides



If we now apply a layout design grid of 80nm to this cell and its boundary, ensuring the centre of each device will be on grid and that minimum poly to poly spacing is not violated, we can analyse the cost in area. (80nm is an arbitrarily chosen value)


Currently, device centre to centre spacing is 390m in the horizontal direction (minimum rule)


  • To snap the devices to an 80nm grid, this spacing would need to increase by 10nm, so that centre to centre spacing would be 400nm (an integer multiple of the design grid).
  • The boundary of each cell would increase in the x axis by 5nm ( Δx=5nm)


The device spacing (centre to centre) in the vertical direction is 680nm


  • To snap the devices to an 80nm grid, this spacing would need to increase by 40nm so that centre to centre spacing would be 720nm.
  • The boundary of each cell would increase in the y axis by 20nm ( Δy=20nm)


From this increase, we can calculate the total area increase


Area Increase = 1 + Δγ + Δx     →     1 + 20nm    + 5 nm       →   1 + 0.029 + 0,0128  → 1.04
                                  γ       x                   680nm     390nm


So there is a 4% increase in area when implementing an 80nm design grid.


Minimum Rule Boundary                                    Design Grid Boundary



It is worth noting that with a different design grid (i.e. 65nm) , Δχ would be 0nm and Δγ would be 17.5nm, leading to a 2.5% increase in area. This increase could be reduced further by either choosing an “on grid” device width (i.e. changing from current width of 210nm to 245nm), leading to no increase in area at all. Optimising schematic designs for adherence to layout design grids, reduces area cost.



Cost analysis – interconnect


 Minimum Rule                                                               Design Grid


Amin = W. Nw + (S x (nW -1))                               Agrid = W.Nw + ( Sgrd X (Nw – 1))

Amin = W.Nw + S.Nw – S                                      Agrid = W.Nw + Sgrid.Nw – Sgrid

Amin = ((W + S) X Nw) – S                                  Agrid =  ((W + Sgrid) x Nw) – Sgrid

For large routing channels ((W + S) x Nw) – S ≈ ((W + S) x Nw) as one wire spacing is small in the grander scheme of things.

Amin = ((W  + S) x Nw)                                      Agrid = ((W + Sgrid)xNw)


Area Increase =  Agrid    →  ((W + Sgrid) x Nw)      →   W + Sgrid

                               Amin            ((W + S) x Nw)                   W + S




  • Width = W; Number of wires (Nwires) = Nw; Spacing = S; Grid spacing = Sgrid


Practical Example:


If we take a practical example of a generic 28nm technology where W=100nm and S=60nm, track spacing, centre to centre would be 160nm. As this is already an integer multiple of the 80nm design grid, Sgrid would also be 60nm, so there would be no increase in area.


However, if we were to choose a different design grid (for example 65nm), track spacing Sgrid, would have to be increased to 95nm (from 60nm) to ensure all tracks were centred on grid.


Area Increase = Agrid      →   W + Sgrid     →   100nm + 95nm    →     1.218

                             Amin                 W + S             100nm + 60 nm



In this case it would lead to a ~ 22% increase in routing area! However it is very important to note, that with increasing metal layer stacks and requirements for minimum and maximum local poly density, most routing now takes place either between the spaced devices and/or over devices, so the requirement for actual routing channels has reduced. Thus the increase in area for routing does not necessarily lend itself directly in an increase in silicon area.


Final thoughts


With the advent of multi-patterning at 20nm and FinFET device pitches at 16nm, the requirements for pitched based, uniform layout designs increases. As’s Mark Lapedus confirmed when discussing 10 and 7nm design, grids are where the industry is going: “There is a general move towards track and grid based layout forms. Expect this trend to increase moving forwards.”




This is a guest post by: Oleg Oncea from IC Mask Design

© Copyright of IC Mask Design

Automotive and IoT Will Drive IC Growth Through 2021

IC sales for automotive systems and the Internet of Things are forecast to grow 70% faster than total IC revenues between 2016 and 2021, according to IC Insights’ new 2018 Integrated Circuit Market Drivers Report. ICs used in automobiles and other vehicles are forecast to generate worldwide sales of $42.9 billion in 2021 compared to $22.9 billion in 2016, while integrated circuit revenues for Internet of Things (IoT) functionality in a wide range of systems, sensors, and objects are expected to reach $34.2 billion in four years compared to $18.4 billion last year, says the new 358-page report.


Between 2016 and 2021, automotive and IoT IC sales are projected to rise by compound annual growth rates (CAGRs) of 13.4% and 13.2%, respectively, compared to 7.9% for the entire IC market, which is projected to reach $434.5 billion in four years versus $297.7 billion last year.  As shown in Figure 1, strong five-year IC sales growth rates are also expected in medical electronics (a CAGR of 9.7% to $7.8 billion in 2021) and wearable systems (a CAGR of 9.0% to $4.9 billion).


Figure 1


Cellphone IC sales—the biggest end-use market application for integrated circuits, accounting for about 25% of the IC market’s total revenues—are expected to grow by a CAGR of 7.8% in the 2016-2021 period, reaching $105.6 billion in the final year of the new report’s forecast. Meanwhile, weak and negative IC sales growth rates are expected to continue in video game consoles (a CAGR of -1.9% to $9.7 billion in 2021) and tablet computers (a CAGR of -2.3% to 10.7 billion), according to the 2018 IC Market Drivers report.


Sharply higher average selling prices (ASPs) for DRAMs and NAND flash are playing a significant role in driving up dollar-sales volumes for ICs in cellphones and PCs (both desktop and notebook computers) in 2017.  Cellphone IC sales are on pace to surge 24% this year to an estimated $89.7 billion, while PC integrated circuit dollar volume is expected to climb 17.6% to $69.0 billion.   For both the cellphone and PC market segments, 2017 will be the strongest increase in IC sales since the 2010 recovery year from the 2009 downturn.  The 2018 IC Market Drivers report’s forecast shows cellphone integrated circuit sales rising 8% to $97.3 billion next year and PC IC revenues growing 5% to $72.6 billion in 2018.


The new report estimates that automotive IC sales will rise 22% in 2017 to about $28.0 billion after increasing 11% in 2016.  Automotive IC sales are forecast to increase 16% in 2018 to $32.4 billion.  Meanwhile, IoT-related integrated circuit sales are on pace to grow 14% in 2017 to an estimated $14.5 billion after increasing about 18% in 2016.  In 2018, integrated circuit sales for Internet of Things end-use applications are expected to rise 16% to about $16.8 billion, according to the 2018 edition of the IC Market Drivers report.



More Information Contact

For more information regarding this Research Bulletin, please contact Rob Lineback Senior Market Research Analyst at IC Insights. Phone: +1-817-731-0424, email: