Monthly Archives: January 2018

TSMC to Invest $19B in a 5nm and 3nm Fab

CPUs are the heart of all the mobile devices we use today, and their performance is paramount to product design and user experience. More efficient processors can lead to more powerful products while maintaining low power consumption. One of the world’s largest chip manufacturers (and consequently processors), TSMC, which manufactures the iPhones processors in recent years, has announced the plan of a new fab in Taiwan to manufacture future chips. TSMC announced that it will manufacture 5nm wafer technology in 2020, and will produce 3nm wafers by 2022.
TSMC is not the first company to announce 5nm technology, since Samsung and IBM (GLOBALFOUNDRIES) already announced such chips during June last year, but the fact that TSMC already announces target dates for commercial production of advanced wafer indicates real progress in the process development.


TMSC plans to invest $17 billion in the company’s new fab.

Highest Performance Interlaken Chip-to-Chip Interface IP Core

Open-Silicon’s eighth-generation Interlaken IP supports up to 1.2Tbps high-bandwidth performance and up to 56Gbps SerDes rates with Forward Error Correction (FEC). This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable, making it ideal for high-bandwidth networking applications, such as routers, switches, Framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data center applications, and several other high-end networking and data processing applications.


The Interlaken protocol is primarily used for high speed chip-to-chip applications. The protocol supports a multiple parallel interface to transmit and receive data from the physical interface or SerDes interface. It also supports packet based interfaces with each packet consisting of multiple bursts, and a simple control work definition to delineate packet and burst boundaries. The protocol is independent of the number of SerDes channels and SerDes rates, and also supports a simple flow control mechanism for back-pressure on any given channel.


The block diagram below shows a functional representation of the multiple aggregate bandwidth interfaces. As an example, a single Interlaken IP instance can be configured in-system to support different Interlaken interfaces: 1×1.2Tbps, 2x600Gbps or 4x300Gbps, leading to a more area efficient and flexible implementation.


Open-Silicon Image 1


Before we dive into further details, it is very important to address the reasons why Interlaken for chip-to-chip communication is superior to other protocols. Interlaken enables a very narrow interface with the use of SerDes channels. Interlaken supports up to 56G SerDes speed and a maximum bandwidth of 1.2Tbps, and is easily scalable to support higher speeds in the future. Interlaken is a channelized interface, which enables multiple sessions and applications to interact at the same time. Interlaken is highly scalable to support N number of SerDes interfaces and also supports different SerDes rates. The Interlaken protocol allows the interleaving of data transmissions or packet transmission from different channels for low-latency operation.


Here are some of the high-level features of Interlaken IP


  • Supports up to 48 lanes of SerDes, and the SerDes rate supported is up to 56Gbps.
  • Supports a maximum bandwidth of 1.2Tbps with a configuration of 24 lanes of 56G SerDes or a configuration of 48 lanes of 25G SerDes.
  • The user interface is a 128- or 256-bit wide segment, and the total number of user segments supported are 8.
  • Features a pipe-based architecture that is easily scalable to support higher speed and bandwidth.
  • Supports both in-band and out-band flow control on different channels with dual and programmable calendar features.
  • Supports multiple aggregate bandwidth interfaces with multiple cores in a single Interlaken IP, allowing the IP to be configured as 1 core, 2 core or 4 core. For example, in a 1.2Tbps configuration, the IP can work as a single 1.2Tbps IP, or it can work as two 600Gbps IP, or it can work as four 300Gbps IP.
  • Supports retransmit capability, thus reducing the overhead on the application to handle retransmit.
Open-Silicon Image 2

Interlaken IP Core – Configurability -One Segment User Interface

Open-Silicon Image 3

Interlaken IP Core – Configurability –Four Segment User Interface

Open-Silicon Image 4
Open-Silicon Image 5

1.2 Tbps Interlaken IP Core
Support for Forward Error Correction [FEC]




Now let us understand, at a very high level, where Interlaken fits in and what the different applications are. The diagram below shows the placement of the Interlaken IP and the medium of communication. The Interlaken IP sits between the customer logic, which sends and receives the packets, and the SerDes IP. The chip-to-chip communication medium could be over a printed circuit board, over a backplane or could be over a cable. To the left of the diagram is a list of a few applications that use Interlaken, such as the packet processing engine (also known as a network processing unit), traffic management chip, switching fabric and switch fabric interface that connects to the switching logic, and framers and mappers. Interlaken is also used in memory chips like TCAM and serial memory. Moreover, almost all of the FPGA guys support the Interlaken interface in their FPGA chips. This is just a short list, but there are many other system applications where Interlaken is used.

Open-Silicon Image 6
  • Packet Processing/NPU
  • Traffic Management
  • Switch Fabric
  • Switch Fabric Interface
  • Framer/Mapper
  • TCAMs
  • Serial Memory (INLK-LA)
  • FPGA etc


Case Study: Data Center System


The left side of the figure below shows a typical data center chassis layout. The line cards and the switch fabric or switch cards are connected to the backplane, and the control/management plane sits at the top. The backplane is a circuit board with sockets that allow line cards and switch cards to be inserted into the socket, connecting them to each other. The line cards provide multiple interfaces to the network. The switch fabric distributes the network traffic across multiple line cards or physical links.


Now let’s look at one piece of the chassis, which is shown in the line card on the right side of the figure. It shows the different chips involved in the line card. Starting from the PHY/optics communicating on the line side; to the framer/mapper to map the SONET/SDH frame to Ethernet and vice-versa; the packet processing/NPU to process the incoming and outgoing Ethernet packets, as well as the TCAM for performing look-ups for the NPU; the traffic management for quality of service; and the fabric I/F to communicate on the system side with the back plane or switch fabric. All of these devices demand very high bandwidth for chip-to-chip communication, and hence, Interlaken is mainly used in such applications.


Open-Silicon Image 7


When compared to available interconnect protocols, Interlaken offers many advantages in scalability, reduced pin count and data integrity. Its channelization, flow control and burst interleaving features make it appropriate for a wide variety of applications. Finally, the availability of a third party IP core minimizes the cost of adopting the new technology and makes Interlaken the obvious choice for next-generation communications equipment.


Comparison of Interlaken IP Products and Features from Open-Silicon

Open-Silicon Image 8


As for the roadmap of Interlaken, customers are demanding ever-increasing ASIC bandwidths, from 600G to 800G to 1.2T. Open-Silicon will continue to broaden its envelope to accommodate these requirements and enable future generations of high-bandwidth networking applications. Open-Silicon is a founding member company of The Interlaken Alliance, which was formed to ensure interoperability between different implementations of the Interlaken protocol. Since 2007 Open-Silicon’s Interlaken IP has been deployed in several different tier-1 networking and computing customer products. Many of these products are shipping in production today in the latest technology nodes in multiple foundries. The unique flexibility and configurability built into Open-Silicon’s Interlaken core meets not only today’s technological requirements, but remains fully compatible with older designs.



This is a guest post by Devendra Godbole and Kalpesh Sanghvi of Open-Silicon.



Semiconductor Shipments Forecast to Exceed 1 Trillion Devices in 2018

Annual semiconductor unit shipments (integrated circuits and opto-sensor-discretes, or O-S-D, devices) are expected to grow 9% in 2018 and top one trillion units for the first time, based on data presented in the new, 2018 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (Figure 1).  For 2018, semiconductor unit shipments are forecast to climb to 1,075.1 billion, which equates to 9% growth for the year.  Starting in 1978 with 32.6 billion units and going through 2018, the compound annual growth rate for semiconductor units is forecast to be 9.1%, a solid growth figure over the 40 year span.

Figure 1

Over the span of just four years (2004-2007), semiconductor shipments broke through the 400-, 500-, and 600-billion unit levels before the global financial meltdown caused a big decline in semiconductor unit shipments in 2008 and 2009.  Unit growth rebounded sharply with 25% growth in 2010 and displayed another strong increase in 2017 (14% growth) to climb past the 900-billion level.

The largest annual increase in semiconductor unit growth during the timespan shown was 34% in 1984, and the biggest decline was 19% in 2001 following the dot-com bust.  The global financial meltdown and ensuing recession caused semiconductor shipments to fall in both 2008 and 2009; the only time that the industry experienced consecutive years in which unit shipments declined.  The 25% increase in 2010 was the second-highest growth rate across the time span.

The percentage split of total semiconductor shipments is forecast to remain weighted toward O-S-D devices.  In 2018, O-S-D devices are forecast to account for 70% of total semiconductor units compared to 30% for ICs.  Thirty-eight years ago in 1980, O-S-D devices accounted for 78% of semiconductor units and ICs represented 22% (Figure 2).

Figure 2

Semiconductor products forecast to have the strongest unit growth rates in 2018 are those that are essential building-block components in smartphones, automotive electronics systems, and within systems that are helping to build out of Internet of Things.  Some of the fast-growing IC unit categories for 2018 include Industrial/Other—Application-Specific Analog (26% increase); Consumer—Special Purpose Logic (22% growth); Industrial/Other—Special Purpose Logic, (22%); 32-bit MCUs (21%); Wireless Communication—Application-Specific Analog (18%); and Auto—Application-Specific Analog (17%). Among O-S-D devices, CCDs and CMOS image sensors, laser transmitters, and every type of sensor product (magnetic, acceleration and yaw, pressure, and other sensors) are expected to enjoy double-digit unit growth this year.

More Information Contact

For more information regarding this Research Bulletin, please contact Brian Matas, Vice President at IC Insights. Phone: +1-480-348-1133, email:
PDF Version of This Bulletin

A PDF version of this Research Bulletin can be downloaded from our website at

Starblaze Reaches Volume Production with Moortec’s Temperature Sensor in their SSD Controller SoC

Moortec, providers of complete In-Chip Monitoring PVT Subsystems today announced that Starblaze Technology have employed Moortec’s 28nm Temperature Sensor IP in their STAR1000 high-end consumer and starter enterprise SSD controller which has recently reached volume production.

Starblaze Technology’s STAR1000 is an enterprise storage SSD controller designed to deliver maximum flexibility and high performance with minimal power consumption while meeting new security requirements for the SSD market.

“We looked at a number of different options for embedded temperature monitoring but decided to choose Moortec’s solution as it not only met but exceeded all our requirements for the project. The Moortec Temperature sensor is highly accurate, easy to integrate and also silicon proven. Moortec also offer a high level of technical support which made the whole process very smooth” said Sky Shen, CEO, Starblaze Technology.

Ramsay Allen, VP of Marketing at Moortec added “We are excited to have been part of this project with Starblaze Technology who are now a key player in the in the field of enterprise chip design with their work on speeding up SSD applications and cloud based client services.”

Moortec’s Temperature Sensor which Starblaze have employed in the STAR1000 is a high precision low power junction temperature sensor that has been developed to be embedded into ASIC designs. It can be used for a number of different implementations including Dynamic Frequency and Voltage Scaling (DVFS), device lifetime enhancement, device characterisation and thermal profiling.

To meet the strict design targets, Starblaze Technology were looking for a selection of IP from highly experienced silicon proven vendors. After evaluating various solutions from a number of providers, Starblaze were confident that Moortec’s high accuracy highly featured Temperature Monitoring IP was the perfect fit for the design and offered everything they needed to meet the power and performance optimisation requirements for their SSD controller.



About Starblaze
Starblaze Technology was founded in November 2015 in China. The company is headquartered in Beijing and has R&D in Shanghai/Chengdu. Starblaze Technology aims to be a world-class enterprise SSD controller/solution design house, speeding up SSD storage applications in data centers, and providing one-stop service from the client to the cloud.


For more information visit the company’s website:

About Moortec Semiconductor
Established in 2005 Moortec provides compelling embedded sub-system IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimization, enabling schemes such as DVFS, AVS and power management control systems. Moortec also provides excellent support for IP application, integration and device test during production.


For more information please contact Ramsay Allen, +44 1752 875133, visit and follow us on Twitter and LinkedIn.


Accurate Performance Analysis Requires Package Modeling

System performance is a critical requirement for the vast majority of integrated circuits that are designed today. To meet these stringent performance requirements, IC designers invest considerable time and effort in accurately modeling and simulating chip level performance – all to avoid nasty surprises when the first chips return from fabrication. Performance modeling and simulation covers a broad range of analyses and tools, including high-level cycle based analysis of top level system blocks and interconnect, power analysis based on interconnect and switching data, static timing analysis to identify critical timing paths, and detailed circuit and electromagnetic (EM) simulations to characterize critical subsystems.


One aspect of performance modeling that is often neglected is package parasitics. Ignoring or only approximating package parasitics can significantly reduce the accuracy of a model, resulting in simulations that fail to accurately identify performance issues prior to tapeout. It could, for example, (1) cause the predicted matching in an RF circuit to be off, (2) cause improper characterization of the expected ground bounce in fast switching, high current circuits, or (3) fail to accurately predict resistive losses in high current circuits. Any of these could result in significant amounts of debug work in the lab. Worse yet, they could lead to an unexpected degradation in performance that is exposed only after the chip is fabricated.


RF circuits aren’t the only circuits susceptible to degradation from the effects of packaging. A large percentage of ASICs and SoCs with fast switching circuits (e.g. DC-DC converters) will be affected, and will benefit from models that include package parasitics.


Modeling Package Parasitics

Properly modeling and simulating package parasitics is key to accuracy, and to first pass success. Intrinsix has substantial accumulated experience modeling various die package types, including wire bond, flip chip, and flip on lead packages. From this, we’ve learned that there are several points to keep in mind when constructing and simulating package models.


Collaboration Is Key

It’s absolutely essential to collaborate with the packaging vendor to construct a model with the required detail. The vendor will be able to provide comprehensive package specifications including diagrams, physical dimensions, and electrical characteristics. The information needed for a package model will depend on the type of package. For flip chips, accurate values for ball height and diameter are required; for bond wires – length and diameter. In addition to information about the package, die thickness of the chip will need to be incorporated into the model as well. Accurate values for these will directly impact the fidelity of the model, and its ability to accurately predict performance related characteristics of the chip.



Illustration 1: 3-D image of IC with lead frame and bond wires


Capable Electromagnetic Modeling and Simulation Environment

Once the packaging information, pin out, and preliminary pad ring have been established, the package model can be constructed.[1] This should be done in the context of a capable electromagnetic (EM) simulator[2] that is able to perform S-Parameter simulations, and can accurately analyze the 3-D EM effects associated with high-speed RF IC packages and bond wires.


Simulation and Modeling Strategies

When performing the EM simulation, there are trade-offs between the range of frequencies that are analyzed versus the time required to perform the simulations. This trade-off should be carefully considered. Failure to analyze a large enough frequency range could result in a missed resonant frequency caused by the package.


Simulation bottlenecks can be avoided by realizing that it’s not always necessary to perform EM simulations on the full package. It’s often sufficient to include just a small subset of critical I/O.  Typically this includes the highest frequency and highest current I/O. Since supply and ground pins will carry the highest current loads, they are usually included in the analysis. Keeping the package model to its essential minimum will allow the simulations to run faster, with fewer convergence issues.


To illustrate the importance of accurate package modeling, consider the S11 plots shown in the diagram below. Each plot illustrates the quality of IC input impedance matching over a range of frequencies, where the best matching is represented by the lowest S-Param values. As can be seen in the diagram, a significant frequency shift can be seen in the narrow band match when simulating with and without the package model. Failure to adequately characterize the matching RF band prior to tapeout can cause expensive debug and rework.


S11 with and without a model of the IC package

Illustration 2: S11 with and without a model of the IC package


Clearly the package can have a large impact on IC performance. At Intrinsix, package modeling and simulation are an integral part of the design flow. In our experience, the effort to develop a detailed and accurate package model is well worth the investment. It will form a solid, accurate basis for exploring and characterizing the performance related behavior of your chip prior to tapeout – reducing the risk of expensive surprises


[1]          Slight changes to the pad ring later in the project may not always impact the model, but care should be taken to evaluate these changes, and update the model if necessary.

[2]          Keysight’s ADS is an example of a capable EM simulator that Intrinsix has experience with



This is a guest post by Chris Bulla of Intrinsix

CEO Talk: JVD Analog ASIC Semiconductors

This interview took place with Bob Frostholm, VP Marketing & Sales at JVD Analog ASIC Semiconductors.



Tell me a bit about your background?


I’ve held Sales, Marketing and CEO roles at established and startup Analog Semiconductor Companies for more than 45 years. I was one of the original marketers behind the ubiquitous 555 timer chip that was introduced in 1972. After 12 years with Signetics-Phillips, Fairchild and National Semiconductor, I co-founded my first startup in 1984, Scottish based Integrated Power, which was sold to Seagate in 1987. I subsequently joined Sprague’s semiconductor operations in Massachusetts and helped orchestrate its sale to Japanese based Sanken Electric, creating what is now known as Allegro Microsystems. In 1999, as VP Sales and Marketing, I rejuvenated sales revenues from $1.5M/qtr to $13M/qtr and facilitated the sale of SEEQ Technology to LSI Logic. I later became President & CEO of PowerX Networks, producing switch fabric chips for network core routers and switches. After the Great Recession, I joined JVD Analog ASIC Semiconductors in 2010. I am also the author of dozens of technical articles and white papers.




How did you first get started with JVD?


I was introduced by a friend. Founder of JVD, Jerry VanDierendonck (see the JVD connection?) had retired for medical reasons and his son Mike had just taken over the business. Mike had run the test operations for the prior 19 years and needed someone to rejuvenate the Marketing and Sales functions that Jerry had previously managed on his own.


Tell me about JVD?


JVD Analog ASIC Semiconductors designs and manufactures Custom Analog ICs for medical, automotive, industrial and consumer applications. These devices challenge standard ASIC design methodology and provide outstanding cost/performance benefits. Founded in June of 1982, JVD has been providing the world with high-quality, cost efficient custom Integrated Circuits for more than 35 years. As a self-funded, debt free, privately owned company, with no shareholders dictating our decisions, everything we do is based on what’s right for our customers and their designs.




When did you start JVD?


Jerry started JVD in 1982 while then employed at LSI Logic. Tired of the company politics and confident that LSI’s inflexible stance on doing only pure digital chips was missing a huge segment of the ASIC market, Jerry wanted to serve the burgeoning Analog segment.


What were you doing before that?


Jerry’s career began at TI. He was fortunate to have been part of the team that developed the world’s first microprocessor, the TMS 1000. Unfortunately, Intel’s patent got reviewed first so they erroneously get credit for being first. The TMS 100 was quite a success and several years later, Jerry and other members of the team decided the future of semiconductors was in Silicon Valley not in the Texas desert. They came in the late 1960s and Jerry worked at CalTex, Litronix and Fairchild, before ending up at LSI Logic.




What problem did you see that needed to be fixed?


While at LSI, Jerry saw the company no bid dozens of great ASIC opportunities that had varying requirements of analog along with the digital. The company had no practical experience in analog and did not want the deviate from its core digital competency. Jerry surmised that in Silicon Valley, with analog kings like National, Fairchild, Signetics, Intersil, Precision Monolithics, and others, that resources would be plentiful. He was right. Linear Technology was 3 years old (1981) and Maxim had been formed the prior year (1983) and the word was that these once staid domains for analog designers was undergoing a mass exodus. Acquiring top talent was easy and thus, JVD was born.



What is your approach to solving that?


Analog products typically sell in lower annual volumes than digital chips. However, the lifetime of the chip is considerably longer. Jerry had to develop a business model that lowered the barrier to entry for companies (NRE & Tooling) to justify the initial costs of development. That successful business model remains in effect today, 34 years later. Over that time frame, JVD has acquired a robust technical team with each member having no less than 25 years of Analog IC Design experience.
Analog IC design is not something that can learned from a book or a few college classes. Expertise comes from years and years of doing it under the mentorship of older and wiser experts. By recruiting only the top tier talent, JVD has amassed a collection of some of the brightest analog guru’s in the world.


How was the role/offering of JVD changed during the recent years?


JVD’s offerings from an application perspective have changed little in recent years. We focus heavily on applications oriented toward medical, industrial, automotive and consumer. What has changed is the manufacturing aspect as todays applications demand smaller size, greater precision and lower noise with reduced power consumption. Many older products still in production today are produced on 0.5um and 0.35um lithography. Most of our newer new designs rely on 0.18um, 0.13um and 0.11um to meet these goals.


Did any of the market consolidation (or acquisition) affected your business and how?


Clearly, the recent rash of semiconductor acquisitions has caused concern for OEMs. Public semiconductor companies are faced with growing pressure, driven by greed from their Boards of Directors and shareholders to continuously grow sales and improve profitability. Profit is good but greed is…. Well, let’s just say “not good”. When two companies merge, each of whom is growing at a market average of 10%, the sum of the two isn’t growing at 20%. The profit driver is the ability to consolidate common functions such as finance, sales, operations, and unfortunately even design. OEM customers know this and tones of M&A strike fear in them. More and more we see requests for integration to remove dependencies on of-the-shelf products that may soon be slated for product obsolescence as a result of mergers.


Another benefit for JVD is the fear that runs through their engineering organizations. Not that the top engineers are worried about being laid off, but they have concerns about reorganizations, working for a new manager, increased and unwanted politics that always comes from an acquisition. These people represent new pools of engineering resources seeking a change and for JVD, that is a very good thing.


Which market segment seems promising to you? And why?


Again, our market focus is Analog with an emphasis on medical, industrial, automotive and consumer. These all remain very positive, high growth segments for us. With the exception of consumer, product lifetimes are relatively long. We have several products now that remain in production after more 20 years.


We don’t try to hitch our wagon to the next flash-in-the-pan. Chasing rainbows is better left for other companies. We are selective about the customers we engage with and the types of products we develop and produce. Better to under commit and over deliver.



What is a typical customer for JVD?


There is no definition of a typical customer for us. We deal with startups all the way to Billion dollar organizations. The commonality they all share is a need to adopt one or more of the primary benefits of a custom analog IC.


  1. Performance Improvement
  2. Lower Cost
  3. Smaller Size
  4. Lower Noise
  5. Lighter Weight
  6. Improved Reliability
  7. Protection of Intellectual Property
  8. Protection from Product Obsolescence
  9. End Market Product Differentiation



Customers are focused on time-to-market, first-time-right, price, etc. Do you see a change in customer behavior in recent years? Where is the focus today and why?


Everyone wants the Holy Grail. Customers today are, for the most part, more educated about analog. Not that they can design a chip, but that they have a far greater appreciation of the complexity…that it is far more complex than digital design. They have a better sense of what they don’t know than say ten years ago…and that’s a good thing. They get the fact that Analog behavior is described by a set of mathematical equations and digital is described by Boolean relations. They are beginning to ask tougher questions about the design and that’s a fantastic step forward.


What are the 3 top things you wish your customers would do better (or different)?


  1. Today’s ASIC customers are quite sophisticated. Occasionally someone wants a combination of functions on a chip that simply cannot be done without violating the laws of physics, but for the most part they understand what they want and why they want it but having a first draft of a specification as a talking point would be extremely beneficial. It needn’t be 100% complete but a page or two as a starting point would be great.


  1. Be wary of the Analog Pretenders. We are always amazed when we hear some of the false promises some customers received by pretenders. I thought our industry had outgrown the idea of making promises, saying whatever the customer wants to hear, in order to get the order. Well, I guess not. If possible it would be great if customers could take more time to ferret out these rascals. Speak directly to the design manager who may be assigned to the project and challenge his or her analog design knowledge and skills.


  1. Understand that real analog design is hand crafted 95+% of the time. The cell library short cut is the kiss of death. If the team you are considering is not well versed (meaning many years of analog IC design… real design, not with libraries…say goodbye and move on.



Are you currently hiring? What type of jobs?


We are always on the lookout for outstanding analog IC designers with more than 25 years of experience directly in the analog domain.



What is your #1 advice for people who want to work for JVD?


Be the best of the best at what you do.



Where can one find more information?



What is the best moment in your day?

Any opportunity to engage in conversation with customers and our design teams is a tremendous learning experience and I never tire of it.



How do you keep yourself energized and engaged during the day?

It’s part of my DNA…I don’t have to do anything…it just comes naturally. (Coffee helps)



What is your preferred lunch discussion topic?




How do you spend your time outside working hours?

My interests include Home Remodeling, Furniture Making & Cabinetry, Amateur Radio, Porsche Club Activities (setting up tours, rallyes and other car events) and last but not least, my Grandkids… I have  3.



Read more about JVD capabilities and services here.