Monthly Archives: June 2018

wafer bumping feature

eWLB

The eWLB (Embedded Wafer Level Ball Grid Array) package technology was developed in cooperation between 3 companies: Infineon, STMicroelectronics and STATS ChipPAC to solve an interconnect problem that was introduced by the fan-in packaging technology (WLCSP).

 

The first eWLB package was used in mobile phones in 2009 and since then it gradually became a viable packaging solution for consumer and wireless ASICs.

 

The Problem With Fan-In Package

 

Fan-In package (or WLCSP – Wafer Level Chip Scale Package) is essentially a bumped die, and hence, it’s the smallest possible package type available today. WLCSP has great benefits: low price, small size, good electrical performance and more. Some applications require high pin count which means very high number of bumps to be placed under the die. This makes the interconnect and the assembly costly and challenging.

 

eWLB Market

 

Today, all the major assembly houses and a few wafer foundries are offering eWLB packaging services. Yole developpement has anticipated the eWLB (Fan-out) market size to increase to USD2.3B in 2022 almost doubling the 2017 market size.

 

 

eWLB Package Technology

 

The main idea behind eWLB is to apply an artificial wafer under the original wafer to create a bigger die area. The artificial wafer is used to connect the die pad to balls (similar functionality to a BGA substrate) – spreading the bumps across a bigger die area allowing more space between the bumps. In eWLB package, the traces are routed outwards (versus inwards in WLCSP).

 

eWLB Assembly Process

 

The eWLB assembly process is performed in wafer level. The wafers are first diced, the dies spaced apart and a resin material is flowed over the dies then hardened to form a re-constituted wafer. The distance between the dies determine the final package outline. Multiple routing layers can be used for complex routing of many pads. The redistribution lines are separate by repassivation layers applied in a manner similar to wafer process back-end passivation.

eWLB Benefits

 

  • Low cost
  • High pin count
  • Great electrical performance
  • Low profile

 

 

2018-MWCS-logo

T2M to showcase cutting-edge Cellular and Low Power Wireless IoT technologies at MWC Shanghai 2018

T2M, the world’s largest independent global semiconductor IP technology provider today announced that they will be showcasing their latest Cellular and Low Power Wireless IoT technology IP at MWC Shanghai on 27, 28 and 29th June at the Shanghai New International Expo Centre.

 

Mobile World Congress Shanghai is the must-attend industry event in Asia. With over 60,000 attendees, the event represents the entire mobile and technology eco-system in areas of: Artificial Intelligence, Automotive, Devices and IoT.

 

At the show, you can experience demos and discuss with T2M experts on our cutting-edge IP:

 

Cellular IOT SoC IP

  • NB-IOT/Cat M1 Phy & PS SW
  • NB-IOT RF IP
  • GNSS SW IP (DSP/CPU)
  • GNSS RF IP & Rx
  • GSM Phy & PS SW

 

Low Power Wireless Connectivity SoC IP Technology (BQB & ZigBee Alliance Certified)

  • BLE v5 / 15.4 Digital LL & MAC
  • BLE v5 / 15.4 RF IP (0.5mm2)
  • BLE v5 SW Stack & Profiles
  • Bluetooth Mesh v1.0 SW
  • ZigBee v3 SW Stack & Profiles

 

When: 27 – 29 June, 2018

 

Location: Shanghai New International Expo Centre

 

To Book a Meeting, Click here.

 

 

About T2M

T2M is the world’s largest independent global semiconductor technology provider, supplying complex IP, software, KGD and disruptive technologies enabling accelerated production of IoT, wireless, consumer and automotive electronics devices. Located in all key tech clusters around the world, our senior management team provides local access to leadership companies and technology. For more information, please visit www.t-2-m.com

ARM_design partner

Black Pepper Spices up the Arm Approved Design Partner Program

ne of the key features of the Arm ecosystem is its open and collaborative nature, and that’s no more evident than in its bank of Approved Design Partners. They bring an additional layer of design expertise and capabilities to SoCs from Arm silicon partners, enabling them with more opportunities to bring custom chips to a vast variety of markets.

 

Ensuring a global spread of design partners, especially around the world’s biggest tech hubs, has always been a priority for us and the addition of India’s Black Pepper is an important milestone on that journey. We now have a trusted design services partner in Bangalore able to support regional APAC licensees within or closer to their respective time zones. India is a hotbed for technology potential, with the government predicting the semiconductor component market alone will be worth more than $30 billion by 2025.

 

Black Pepper: Making Arm-based ideas a reality

 

In addition to providing a design services route for Arm IP in India, Black Pepper also has a presence in Singapore and will soon expand to North America. In the company’s own words: “Give us a barely-there idea – captured perhaps on nothing more than a white-board – and we can transform it into a form-factor-ready product, fully manufacturable and ready to be drop-shipped in high volumes”.

 

A dozen tier-1 semiconductor companies utilize Black Pepper’s turnkey solutions which range from initial logic design to embedded software solutions and into post-design expertise including silicon validation, yield optimization and supply chain management.

 

Keeping the ecosystem open

 

For our ecosystem to continue to share success, we need to ensure the right partners have access to Arm IP at the right time, whether this is enabling design houses to work well with Arm IP, or making access to this IP easier, faster and more cost effective.

 

Arm established the Arm Approved Design Partner program in 2016 as a way of providing assurance that companies offering design services around the Arm architecture have the experience, quality systems and resources in place to develop Arm-based SoCs. It was a way of ensuring a healthy ecosystem of providers, with a guarantee of quality and support from Arm. Arm purposefully chose not to build its own System-on-Chip (SoC) design services team as we believe that an openly competitive ecosystem makes for a more innovative environment.

 

With ten approved partners now and more on the way, we believe this is a robust model for the IoT market in particular, as cost and time to market pressures keep increasing.

 

Meanwhile, to further help companies that want to build custom SoCs there’s Arm DesignStart, a web portal which enables companies to quickly access technology such as the Cortex-M0 and Cortex-M3 processors through a simple contract, with no upfront fee, and a success-based royalty model.

 

What is the Arm Approved Design Partner Program?

 

Chip implementation can be easily outsourced to one of many design service companies. These companies provide services across the custom SoC design process, allowing a company to outsource any part of a project – including chip manufacturing and supply.

 

The Arm Approved Design Partner Program is open to all System-on-Chip (SoC) design services companies. It provides low cost access to Arm IP so that these design houses can gain experience, together with the assurance provided by Arm that they have expertise in working with the Arm architecture.

 

Those services companies offer can include:

  • Full custom chip life cycle management from specification to working silicon
  • Providing engineering resources to augment your own design team
  • Functional & physical design/verification services

 

 

About Arm

Arm technology is at the heart of a computing and connectivity revolution that is transforming the way people live and businesses operate. Our advanced, energy-efficient processor designs have enabled the intelligent computing in more than 125 billion chips. Over 70% of the world’s population are using Arm technology, which is securely powering products from the sensor to the smartphone to the supercomputer. This technology combined with our IoT software and device management platform enable customers to derive real business value from their connected devices. Together with our 1,000+ technology partners we are at the forefront of designing, securing and managing all areas of compute from the chip to the cloud.

Silicone wafers in a carrier

Semiconductor Market Size – History and Forecast

The semiconductor industry is in constant growth and has a very promising future.  Industry’s market experts have agreed the market size will grow even more in next decade. Some believe the IoT and Automotive market segments are the key growth and will eventually change our lives forever. After all, semiconductors are crucial components of electronics products.

 

Year 2017 was the first-time semiconductor revenue has surpassed $400 billion. The market reached the $300 billion milestone seven years ago, in 2011, and surpassed $200 billion in 2000.

 

Worldwide semiconductor revenue is forecast to total $440 billion in 2018, an increase of 7 percent from 2017. In addition, we estimate the worldwide semiconductor revenue to reach $440 billion in 2019.

 

The following chart shows the semiconductor market size from 1999 to 2017. During that 19 years the market size has more than doubled thank to the prolific mobile and consumer market.

 

Memory market segment has been very profitable in the last year (2017). Today, every device has memory content:  RAM and Flash. In the last 12 months, a shortage in memory devices has created higher margin and profit leading to a booming semiconductor market.

semiconductor market size history and future anysilicon

 

To download the chart please click here.

 

DAC

Elsys exhibits at Design Automation Conference 2018

Elsys with its comprehensive digital and mixed-signal SoC services and solutions stands for a reliable and agile design services company. Recognized on the market for its expertise and stability, Elsys has become a proud partner of Arm and IAR Systems.

 

Known for its best-in-class engineering support in domains of digital, analog and mixed-signal design, verification, custom layout, IP and silicon validation services and software development, Elsys main goal is to support clients on their path to business excellence. Moreover, to provide customers with essential support in order to overcome any design engineering challenges related to resources and time to market pressure.

 

If Elsys resembles the values you strive for in business partners, stop by Elsys booth 2256, at DAC from June 25-27th in Moscone Center, San Francisco.

 

Special attention at DAC 2018, booth 2256, Elsys will dedicate a presentation of their custom SoC design service solutions endorsed by Arm. Additionally, the focus will also be on the way Elsys assist their customers in order to establish the right mixture of support, expertise and technical know-how to develop innovative and differentiated products in their targeted applications, such as IoT.

 

When: 25-27 June from 10:00 am to 6:00 pm

Location: Moscone Center, San Francisco, CA

Booth#: 2256

 

To set-up a Meeting, email Pascal Barioulet  pb@elsys-america.com

For more information about DAC conference, visit https://dac.com/

 

About Elsys

Elsys America based in Sunnyvale, California, supported by 19 design centers across Eastern Europe (Serbia), France and US, and empowered by 600 top-notch engineers offers semiconductor design services and solutions in areas of: digital and analog/mixed-signal design, verification, analog modeling, layout, silicon validation, and embedded software. As a preferred provider and partner of top-tier semiconductor companies in Automotive, Industrial, IoT and Telecoms, we are known for helping our customers find resources or expertise they require in the most efficient and cost-effective way. Discover more at  http://www.elsys-america.com/

 

Contact Information:
Pascal Barioulet

Elsys America
pb@elsys-america.com
+1 669 221 9890 (Cell)

 

 

DAC

Faraday Exhibits AI FPGA-to-ASIC Solution and IoT SoC Platform at DAC 2018

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that it will showcase their AI FPGA-to-ASIC solution and the Uranus+™ ultra-low-power IoT SoC development platform at Design Automation Conference (DAC), June 25-27, 2018 in San Francisco, CA, USA.

 

Faraday’s FPGA-to-ASIC conversion service has successfully completed several AI related projects including drone vision, medical image analysis, smart appliances, and 3D sensing. It brings remarkable power savings, enhanced performance, and lower system cost to meet specific AI requirements. By leveraging a comprehensive IP solutions suite and advanced FinFET process nodes, the service is particularly well suited for AI chips requiring higher bandwidth and a lower latency interface.

 

The demonstrated Uranus+ platform is a 32-bit MCU-based ultra-low-power SoC with embedded flash, implemented by UMC 55ULP technology, targeting to accelerate the development of IoT applications. It features DVFS power modes management to balance trade-offs between performance and power consumption. In particular, its Turbo Mode enables MCU core to achieve 2x performance under same operating voltage.

 

 

Uranus+ IoT SoC Development Platform – DVFS Operation Modes

 

“We are very excited to present our latest ASIC solutions at DAC,” said Flash Lin, Chief Operating Officer of Faraday. “Founded since 1993, we position ourselves as the driver of ASIC design service innovation. As the demand for AI ASIC chips is growing, we look forward to exploring more opportunities at the show and building strong business relationships in the US.”

 

Visit Faraday’s booth at #2138 and find out the latest solutions from Faraday.

 

Evan Ke
886.3.5787888 ext. 88689
evan@faraday-tech.com