Monthly Archives: July 2018

karel codasip

CEO Talk: Karel Masařík

This interview was held with Karel Masařík, Founder and Chief Executive Officer at Codasip, Ltd.

 

 

Tell me a bit about your background. How did you first get started with your company?

 

Codasip was born a decade ago out of my PhD work at the Technical University of Brno. I earned an internship at a German automotive company that was ahead of its time in the development of display camera mirror replacement technology. They were trying to solve a difficult problem that needed a customized compute solution. The internship led to paid customers and Codasip was created within the TU Brno incubation program.

 

Tell me more about Codasip.

 

Codasip has been around since 2014. The company is a provider of both processor development and design tools, and a licensor of implementations of RISC-V cores. We use our own tools to create a broad portfolio of processors. We are headquartered in Brno, Czech Republic, and we have an office in Silicon Valley and soon also in China.

 

RISC-V (pronounced “risk-five”) is an open processor instruction set architecture (ISA) that can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in both high-performance computing and low-power embedded applications. It also has a growing software ecosystem driven by a community of users. The architecture originated in 2010 at the University of California, Berkeley, but many contributors are volunteers and private industry engineers.

 

What problems did you see that needed to be fixed? What is your approach to solving them?

 

We recognized the commercial potential of RISC-V early on. It was evident that the industry wanted more choices in processor IP, and that what was needed was high-quality, fully verified, and professionally supported cores if RISC-V was ever going to successfully make it out of academia. It is a bit like Linux, in that it was not taken seriously in the IT world until companies like Red Hat provided the OS in physical media with documentation and technical support.

 

How has the role and offering of Codasip changed during the recent years?

 

We started out as an EDA company, promoting our core technology to companies wanting to create their own proprietary processor technology. However, that is a relatively small market, with few processor geniuses in the world who want to roll their own IP. But since we were processor guys, we created and licensed our own RISC architecture before eventually making a strategic shift to embrace the best that RISC-V has to offer.

 

So today, Codasip aims to have the most comprehensive portfolio of RISC-V processor IP in the industry. The Codasip Studio tools allow us to continually bring new cores to market in a timely fashion, giving us a unique competitive advantage.

 

We simplify the process of tailoring a processor solution by putting the power of our technology into the hands of customers, allowing them to build their own unique RISC-V processor that is just right for their application.

 

Which market segment seems promising to you? Why?

 

We are very excited about the use of our technology by customers in machine-learning applications like inference engines, in offload, and in smart sensor and IoT networking. There are many companies doing innovative things in these areas and it makes our jobs pretty exciting.

 

Who is a typical customer of Codasip?

 

Our customers are primarily fabless semiconductor companies or systems companies that design their own chips for internal consumption. They are looking for ways to differentiate, and our tools allow them to build processors that are 100% unique to them. We help them create their own IP.

 

Are you currently hiring? What type of jobs?

 

Definitely! We are always looking for talented engineers in areas like software, compiler, and RTL verification specialists.

 

Where can one find more information?

 

Visit our website at www.codasip.com, or learn more about the RISC-V technology and community at www.riscv.org.

 

What is your preferred lunch-discussion topic?

 

When not discussing work, we like to talk about ice hockey and which pubs in Brno have the best pilsner beer!

 

How do you spend your time outside working hours?

 

I have a beautiful 3-year-old daughter who keeps me busy and away from my laptop when I’m at home.

 

Check out Codasip’s profile page on AnySilicon by clicking here.

 

news

Sankalp Semiconductor Appoints Sathish Kumar Ganesan as Vice President Engineering

Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, has appointed Sathish Kumar Ganesan in the key position of Vice President Engineering for IP Business. In this capacity, Sathish will be responsible for IP development and related engineering services. He has 16+ years of experience in the semiconductor industry with expertise on AMS IP, MAC & SoC designs. Sathish has worked with various organizations like Cadence, Cosmic Circuits, Cypress Semiconductor and Samsung Electronics. Sathish has Masters in VLSI CAD from Manipal University. He holds 3 patents and has published multiple international papers/journals.

 

“Sathish’s induction to the team will enable accelerated growth of IP and related services for Sankalp.” said Samir Patel, CEO Sankalp Semiconductor. “His experience and energy make him an ideal choice for this important position.”

 

“Sankalp Semiconductor has an excellent team of talented engineers that will continue to drive Sankalp forward as the leader in design services & custom IP solutions,” said Mr. Ganesan. “My focus will be to work closely with customers to deliver high quality IP solutions & services.”

 

Sankalp Semiconductor has executed multitude of complex digital and mixed signal SoC (System-on-Chip) projects for variety of its customers in Automotive, Consumer, Networking, Wireless, IoT, Medical, Foundry verticals. Sankalp Semiconductor was founded in 2005 with a focus to serve the semiconductor companies primarily offering analog & mixed signal design services. Today, Sankalp with a team of 800+ engineering professionals has design centers in Hubli, Bengaluru, Kolkata and Ahmedabad in India and Ottawa, Canada. The company provides unique advantage to its semiconductor customers by enabling them to engage at any point of semiconductor services life cycle with the ability to provide end-to-end solutions.

 

 

About Sankalp Semiconductor

Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers achieve their time-to-market window by delivering first time right silicon designs and engage with product engineering teams across the globe to design System-on-Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia. www.sankalpsemi.com

 

 

Contact Information:
Eklovya Sharma

Sankalp Semiconductor
marcom@sankalpsemi.com
+91 98790 48571 (Cell)

 

amkor smart package

Amkor Delivers Industry’s First Package Assembly Design Kit to Support Mentor’s High-Density Advanced Packaging Tools

Amkor Technology announced today it has partnered with Mentor to release Amkor’s SmartPackage™ Package Assembly Design Kit (PADK), the first in the industry to support Mentor’s High-Density Advanced Packaging (HDAP) design process and tools. Amkor’s award-winning High-Density Fan Out(HDFO) process can now be used in conjunction with Mentor’s software to deliver early, rapid and accurate verification results of advanced packages required for Internet-of-Thingsautomotive, high-speed communicationscomputing and artificial intelligence applications.

 

 

“Amkor leads the way in HDFO technology for OSAT companies, and with the rise of complex ICs with multi-die packages, we prioritized the creation of Mentor-based PADKs to significantly reduce cycle time,” said Ron Huemoeller, corporate vice president – research & development, Amkor Technology. “Since the Mentor flow includes Calibre, the golden sign-off tool for the fabless ecosystem, our customers can easily close any physical verification issued for their entire solution.”

 

 

The complex and compact design of devices for today’s smart applications is driving the need for sophisticated packaging techniques such as heterogeneous integration and Advanced System-in-Package. These solutions combine one or more ICs of different functionality with increased I/O and circuit density in 2.5D (side-by-side) and 3D constructions. With Amkor’s SmartPackage PADK and Mentor’s proven HDAP tool flow, mutual customers of Amkor and Mentor have the ability to create and review multiple assemblies and LVS (layout vs. schematic), connectivity, geometry and component spacing scenarios using Amkor’s HDFO process. The graphic environment features robust data and is straightforward to use before and during the implementation of physical design, resulting in faster sign-off and fewer verification cycles.

 

 

“Amkor was the first OSAT company to join the Mentor OSAT Alliance program, and now the first to build and make available a PADK for its customers,” said AJ Incorvaia, vice president and general manager of Mentor’s BSD division. “By providing a fully validated PADK for Amkor’s HDFO process for Mentor’s proven HDAP tool flow, customers can more easily transition from classic chip design to 2.5 and 3D solutions.”

 

 

The OSAT Alliance program helps promote the adoption, implementation and growth of HDAP throughout the semiconductor ecosystem and design chain, enabling system and fabless semiconductor companies to have a friction-free path for emerging packaging technologies.

 

 

For additional information, please contact us at Sales@amkor.com

 

latest-news

Open-Silicon and Credo Demonstrate Solutions for Deep Learning and Networking Applications at TSMC OIP and Symposium in Amsterdam

pen-Silicon, a system-optimized custom SoC solution provider and long-standing member of TSMC’s Value Chain Aggregator (VCA) and Design Center Alliance (DCA) programs, and Credo, a global innovation leader in Serializer-Deserializer (SerDes) technology, will participate in a joint demonstration at the TSMC 2018 Open Innovation Platform Ecosystem Forum and Technology Symposium in Amsterdam, The Netherlands. These demonstrations will illustrate the capabilities of Open-Silicon’s High Bandwidth Memory (HBM2) IP subsystem and Credo’s 56G SerDes IP in enabling deep learning and networking applications. Visitors will also learn about other critical IP cores required for these applications, including a RISC-V based CPU subsystem, and Interlaken IP and Ethernet IP subsystems.

 

Open-Silicon’s HBM2 IP subsystem solution, in TSMC’s FinFET and CoWoS® technologies, includes an HBM2 controller, PHY and interposer I/O. It’s architected and designed to provide the highest performance and flexibility for integrating high bandwidth memory directly into next-generation custom SoC 2.5D SiP solutions. Credo’s high-speed 56Gbps PAM4 LR Multi-Rate SerDes and 112Gbps PAM4 MR/LR SerDes in TSMC’s FinFET technologies is targeted for next generation high performance computing and networking SoCs.

 

“This collaborative demonstration with Credo is an excellent opportunity to unveil the power of a complete end-to-end solution for the next generation of deep learning and high-performance networking applications,” said Shafy Eltoukhy, SVP of Operations and GM, Open-Silicon. “Having representatives from both companies in one place also presents an opportunity for attendees to discuss their ideas and unique design requirements.”

 

“Credo’s silicon proven 56G/112G SerDes IPs, combined with Open-Silicon’s SerDes Technology Center of Excellence, can minimize risk and time-to-market for developing the next generation of networking and data center custom SoCs,” added Jeff Twombly, Vice President of Business Development at Credo.

 

When: July 23, 10:30 a.m. to 6:30 p.m., and July 24, 8:30 a.m. to 5 p.m.

 

Where: Ecosystem/Partner Pavilion, Hilton Amsterdam Airport Schiphol

 

About Open-Silicon
Open-Silicon is a system-optimized custom SoC solution provider. To learn more, visit www.open-silicon.com

 

About Credo
Credo is a leading provider of advance SerDes IP. To learn more, visit www.credosemi.com

Market Research

Semiconductor Content in Electronic Systems Forecast to Reach 31.4% in 2018

In its upcoming Mid-Year Update to The McClean Report 2018 (to be released at the end of July), IC Insights forecasts that the 2018 global electronic systems market will grow 5% to $1,622 billion while the worldwide semiconductor market is expected to surge by 14% this year to $509.1 billion, exceeding the $500.0 billion level for the first time.  If the 2018 forecasts come to fruition, the average semiconductor content in an electronic system will reach 31.4%, breaking the all-time record of 28.8% that was set in 2017 (Figure 1).


Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (-1%), automobiles (3%), and PCs (-1%) forecast to be weak in 2018, the disparity between the moderate growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

 

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2018 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and average electronic system sales growth this year. After slipping to 30.2% in 2020, the semiconductor content percentage is expected to climb to a new high of 31.5% in 2022.  IC Insights does not anticipate the percentage will fall below 30% any year through the forecast period.

 

The trend of increasingly higher semiconductor value in electronic systems has a limit.  Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4%-5% per year).

 

The 250+ page Mid-Year Update to the 2018 edition of The McClean Report further describes IC Insights’ IC market forecast data for 2017-2022.

Report Details: The 2018 McClean Report
Additional details on the IC market forecast and other trends within the IC industry will be provided in the Mid-Year Update  to The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. A subscription to The McClean Report includes free monthly updates from March through November (including a 200+ page Mid-Year Update, and free access to subscriber-only webinars throughout the year. An individual-user license to the 2018 edition of The McClean Report is priced at $4,290 and includes an Internet access password.  A multi-user worldwide corporate license is available for $7,290.

More Information Contact

For more information regarding this Research Bulletin, please contact Bill McClean, President at IC Insights. Phone: +1-480-348-1133, email: bill@icinsights.com

 

PDF Version of This Bulletin

A PDF version of this Research Bulletin can be downloaded from our website at http://www.icinsights.com/news/bulletins/

tsmc

Inomize to present a paper at TSMC OIP Forum in Amsterdam

Inomize, a leading Israeli design services company, will present a paper at TSMC OIP Forum in Amsterdam, The Netherlands on Monday 23rd July, as well as exhibiting at the OIP Forum and the TSMC Symposium on Tuesday 24th July.

 

Abstract: Based on TSMC 16n FFC automotive process design of a multi processors System on Chip to be part of autonomous driving solution.

 

The design aim to meet ASIL B safety level with some specific design island that were qualify to ASIL D. Architecture of the chip supports very high bandwidth from all processors to 2nd level cache and DDR while applying end to end error correction and transaction monitoring with special design of Network on a Chip with safety wrapper on each port whether it is master or slave (85 ports). All on chip memories were design to add check and remove error correction code on data and address with specific flow that aggregates all errors and support in system memory BIST as well as production tests. In order to support layout of a huge design tradeoff of operational frequencies and bus width were done to ensure high yield and performance as well as asynchronous data pipes over long data paths. Secure Boot process that cannot be breached in any test mode and seal all data paths to be open step by step with cryptographic signatures embedded with on chip functional test LBIST and MBIST procedures. Process and temperature monitor to improve safety and reliability during lifetime of the product.

 

 

About Inomize:

 

Inomize is a professional Research & Development firm specializing in the design and delivery of hardware solutions. Inomize offers a wide range of services tailored to meet your project needs and product constraints in terms of cost, performance and power consumption.

 

Inomize successfully delivers ambitious projects on time and on budget. Inomize gets the maximum out of the available technology and, when necessary, push it to the limits using the latest advancements to meet customer’s project needs. With years of experience and a proactive project management approach, Inomize reduces development time and minimizes risks of complex hardware design projects.

 

Established in 2007, Inomize is a fast-growing company and one of the largest ASIC design firms in Israel. Among Inomize’s customers are large international corporations and startup companies from Israel, Europe and North America.

 

Find out more about Inomize at www.inomize.com

 

 

TSMC Europe (Amsterdam) Technology Symposium:

July 23th-24th, 2018:

Hilton Amsterdam Airport Schiphol

Amsterdam, Netherlands

 

 

For further information, please contact:

David Wolf

VP Business Development

Inomize Ltd.

Phone:  +972-72-277-5400

E-mail: dudiw@inomize.com