Monthly Archives: September 2018

growth market

MCUs (Microcontrollers) Sales History and Forecast 2016-2022

MCU sales and units shipments driven by the spread of embedded control in systems, more sensors, and the rush to connect end-use applications to the Internet of Things (IoT).

The market for microcontrollers—the IC industry’s original system-on-chip (SoC) product category—is expected to continue hitting record-high annual revenues through 2022 after worldwide sales dropped 6% in 2016 because of a slowdown in MCU unit shipments. After drawing down MCU inventories in 2016, systems manufacturers stepped up purchases of microcontrollers in 2017 with unit shipments surging 22% and strong growth continuing in 2018.  In its Mid-Year Update to The 2018 McClean Report, IC insights raised its projection for MCU shipments to 18% in 2018 with the unit volume reaching nearly 30.6 billion. MCU revenues are now forecast to rise 11% in 2018 to an all-time high of $18.6 billion, followed by 9% growth in 2019 to about $20.4 billion (Figure 1).

Figure 1


The Mid-Year Update also raised the five-year growth projection of MCU sales to a CAGR of 7.2%, reaching nearly $23.9 billion in 2022, with unit shipments increasing by a compound annual growth rate of 11.1% to about 43.8 billion in the final forecast year.

The ASP for microcontrollers fell to the lowest point ever in 2017 and prices are continuing to drop at about the same rate in 2018. However, the annual rate of decline has eased in the last five years compared to earlier this decade.  IC Insights’ new forecast for MCU ASP shows the average selling price falling by a CAGR of -3.5% in the 2017-2022 period, much slower than the -5.8% decline seen during the 2012-2017 period and the 20-year CAGR of -6.3% between 1997 and 2017.

A key factor in the 2017 recovery of MCU sales from the decline in 2016 was a turnaround in the smartcard microcontroller segment. About 40% of total MCU shipments are currently for smartcard applications, but that is down from about half early in this decade. Excluding smartcard MCUs, sales of “general” microcontrollers for embedded systems, automated control, sensing applications, and IoT-connected things are forecast to grow 11% in 2018 to $16.4 billion after rising 14% in 2017.  Shipments of general MCUs are projected to climb 25% in 2018 to 18.9 billion units after rising 21% in 2017.   General microcontrollers now represent a little over 60% of MCU unit shipments and are forecast to reach 68% of the total in 2022.  Currently, general MCUs generate about 88% of total microcontroller revenues, and they are expected to reach 90% of the entire market value in 2022.

Across nearly all MCU applications, strong growth in 32-bit microcontrollers has reshaped the market as suppliers aggressively promote more powerful designs that are cost competitive with 8-bit and 16-bit devices, which have typically been used in consumer products and other high-volume systems.  In some cases new 32-bit MCUs are being priced below the cost of 8-bit microcontrollers.  On average, 32-bit MCUs were selling for about twice the amount of the ASP for all microcontrollers in 2012 ($1.76 for 32-bit versus $0.88 for total MCUs).  In 2018, the ASP for 32-bit MCUs is expected to be just $0.09 higher than the ASP for all MCUs, and by 2022, the difference is forecast to shrink to $0.05 ($0.60 for 32-bit versus an average of $0.55 for total MCUs).

Report Details:  The 2018 McClean Report
Additional details and trends within the IC industry are provided in The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2018).  A subscription to The McClean Report includes free monthly updates from March through November (including a 200+ page Mid-Year Update), and free access to subscriber-only webinars throughout the year.  An individual-user license to the 2018 edition of The McClean Report is priced at $4,290 and includes an Internet access password.  A multi-user worldwide corporate license is available for $7,290.


To review additional information about IC Insights’ new and existing market research reports and services please visit our website:



More Information Contact

For more information regarding this Research Bulletin, please contact Rob Lineback, Senior Market Research Analyst at IC Insights. Phone: +1-817-731-0424, email:


PDF Version of This Bulletin

A PDF version of this Research Bulletin can be downloaded from our website at

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How to Calculate your ASIC Unit Cost

Finding your ASIC unit cost is one of the most important steps prior starting any ASIC design activities. If you are a semiconductor company – your company’s profit is highly depended on the ASIC production cost. This guide will help you understand the different cost components related to the ASIC manufacturing.


In today’s competitive market, profits or losses must be estimated from day one. Moreover, if you are shipping products into a competitive market, your ability to reduce cost will determine your success in the short and long run.


The two major components in ASIC costs are:


  • ASIC development costs
  • ASIC unit cost


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The concept described in this guide is applicable both for small ASICs (such as BlueTooth or IoT chips) and for large chips such as Crypto ASICs or networking chips. This paper will focus only on ASIC unit cost


ASIC Unit Cost Breakdown


ASIC manufacturing costs includes: wafer cost, assembly cost and test cost. While there are additional related costs, these three components cover 95% of any ASIC cost.


Yield is also a key component of ASIC cost that is often overlooked in early stage price calculation. There are three types of yield figures: wafer yield, assembly yield and test yield. You want, of course, the yield to be as high as possible.


The following table describes the different ASIC cost components:



Silicon Die Cost


The first component in the finished ASIC production cost is the silicon die cost.


We start with calculating the number of dies per wafer (DPW). AnySilicon provides a simple die per wafer (DPW) calculator that can help with this task.


Input: die size (x,y)

Output: dies per wafer (DPW)


Once the number of dies per wafer is available, it is possible to divide the wafer price with the DPW figure to find the die cost.


If the die size is not available at this stage of the project, you can assume a few sizes to get best-case and worst-case scenarios.



Wafer Test Cost


Testing each die is time consuming and therefore introduces a price adder to the total ASIC cost, but in some cases it is necessary. The price of wafer testing is corelated to the number of seconds the test is performed.


Wafer testing is based on renting test machines. This means that as a customer, you are paying for renting the Automated Test Equipment (ATE) and the wafer prober to test your silicon.


If the tester hourly rate is (for example) $100 and the test duration is 1 second. Your wafer test cost will be: $0.0278 per chip.


The wafer yield figure will be available when wafer sort is completed.


Packaging Cost


Whether your chip is assembled in a QFN or a WLCSP package type, you need first to collect all the costs associated with the assembly process. This may include:


  • Wafer back-grinding (thinning)
  • Dicing of wafer (singulation)
  • Substrate material (in case of BGA package)
  • Assembly/package cost


Here too, like in wafer testing, you end up with an assembly yield figure that impacts the ASIC production cost. The typical figure for assembly yield is 97%-99%.


Final Test Cost


All ASICs need to go through a quality test before they are shipped to customer. Therefore, every ASIC supply chain ends with a Final Test. It’s an automated electronic test that screens the good and the bad chips.


Like with wafer testing, your cost is based on renting the test equipment from the vendor and paying per hour while the vendor operates the test for you.


If the tester hourly rate is, for example, $100 and the test duration is 1 second. Your final test cost will be: $0.0278 per chip.


The ASIC yield figure will be available when final sort is completed.


Supply Chain Cost


This is the (shipping cost of the material from one site to another. From example from the wafer fab to the assembly house. And the labor cost of managing the supply chain: planning the supply chain, sending invoices, reacting to various issues or problems etc.


Putting it All Together – Crypto ASIC Price Example


The following table shows an example for a Crypto ASIC price breakdown. For simplification reasons we have ignored the wafer sort in this example.



amkor taiwan

Amkor Opens New Semiconductor Package Manufacturing and Test Plant in Taiwan

Amkor Technology announced on September 10th the opening of its new manufacturing and test plant at Longtan Science Park in Taiwan.

“Demand for Amkor’s advanced assembly and test services in Taiwan continues to increase.  The opening of our fourth factory in Taiwan will allow us to keep pace with that demand,” said Steve Kelley, Amkor’s president and CEO. “Our new Longtan facility will focus on wafer probe and die processing, complementing the wafer-level and other advanced packaging capabilities of our other three factories.”


The new facility is Amkor’s first manufacturing plant in Longtan Science Park, which is well known for incubating Taiwanese high-tech businesses, including those in the semiconductor industry. The Science Park has strict environmental protection standards and only companies that are in full compliance are permitted. Amkor is also seeking ISO 15408 Common Site Criteria certification for the Longtan plant to ensure rigorous security protection during the manufacturing process.

“I am pleased to announce the opening of our new factory in Longtan, which enters its production phase this month,” said YongChul Park, Amkor’s executive vice president, Worldwide Manufacturing. “This expansion signifies Amkor’s ongoing commitment to invest globally and showcases our ability to leverage resources internationally.”


Below are photos taken during Monday’s opening ceremony at Amkor’s new Taiwan factory.






Depositphotos_87180538_l-2015 small

SoC Timing ECO Cycle

Timing ECOs refer to last mile timing and DRC fixes before you tape-out the ASIC. EDA implementation tools (with help of physical design engineers) do 95-98% of the job when it comes to meeting the timing goals. For the last 1-2% timing violations, however, it is prudent to handle them manually in a more deterministic manner rather than pushing the EDA tools- which may take a longer time to converge, if not entirely give up! Designers need to give a great deal of thought while doing these timing ECOs, in particular, the order in which they should go about fixing the problems. Here’s the recommended order:


  1. DRC/DRV Fixing: Design Rule Checks (DRCs) or Design Rule Violations (DRVs) usually refer to max_transition and max_capacitance limits set either by the timing libraries, or some tighter values explicitly defined by the designers. We need to fix these to prevent any extrapolation while computing the cell delays from the look-up tables in the timing libraries where the EDA vendor doesn’t guarantee the delay numbers reported by the timing or optimization tools.The first and the foremost fix to start with is the clock fixes. The reason being any changes on the clock path will impact your data path timing by changing the setup or hold windows. Among clock fixes, you can choose to fix clock max_capacitance first or clock max_transition Fixing one would invariably fix the other. Also note that going with the library limit for max_capacitance or max_transition might result in increased internal power dissipation, and designers usually tend to decide on the max_transition limit based on the basis of a certain percentage of clock period, say, 10%.


Transition violations can be fixed by either by upsizing the driver, or perhaps splitting the net by insert a buffer which would effectively split the load driven by a cell and hence improve transition. Buffer insertion would also help fixing max_capacitance violations as well.


After clock DRV fixing, you can perhaps do a data DRC/DRV fixing.

  1. Setup Fixes: There are many different ways you can fix setup.
    1. Vt swapping: Swapping the higher Vt (threshold voltage) cells to lower Vt cells can help reduce the delay, at the expense of higher leakage power.
    2. Upsizing the cells: Upsizing the cells might also help in improving the delay of cells along a timing path, however, one needs to be cautious. If you upsize an x1 cell to let’s say an x12 cell you run into the risk of increasing the load on the previous cell, thereby degrading the overall timing path. This can also result in local IR drop issues as well, because bigger cells would tend to draw more current from the power grid as compared to the smaller cells.
    3. Sizing cells on the side branch: If you have one cell driving let’s say 3 cells and out of these 3 cells, you have positive setup slack on 2 branches (side loads), while at least 1 fan-out is violating setup, you can try to downsize the cells along the branches with positive setup slack. This will reduce the loading on the buffer, and thereby help improve setup timing on the first fan-out as well.
    4. Useful Clock Skew: This elongates the window for signal arrival by pushing the clock to the capturing sequential. This method may create hold violations on the same capturing flip-flop, or perhaps even setup violations on the path originating from the capture flip-flop.


  1. Power Recovery: There are a couple of ways you could attempt to recover power by either
    1. Downsizing the cells to save dynamic power.
    2. Swapping the lower Vt cells to higher Vt cells to save leakage power.


Before you even proceed with power recovery, you need to obtain the list of cells failing IVD (Instantaneous Voltage Drop) or dynamic IR drop. One would need to first downsize the cells in the vicinity of the IVD failing cell before attempting dynamic or leakage power recovery because of 2 reasons:


  1. IVD failure is a must-to-fix check because it can result in timing failures on silicon, while dynamic/leakage power recovery is a good-to-have check because it makes your device dissipate lesser power. You would want to start with a fix that’s more critical.
  2. More importantly, if you go about downsizing cells to recover dynamic power first, you eat up all the positive slack in your timing paths. Subsequently, if you downsize cells failing IVD, you would see a surge in your timing violations and it will be very difficult to fix these timing paths again.


Therefore, ideal approach is to do downsizing cells in the vicinity of IVD failing instances, and then downsize the cells along a timing path if you still have a positive slack, or else upsize the cells along the timing path if you are violating setup.


Now back to power recovery. Among downsizing and Vt swapping, which one would be better to do first? The answer may vary from design to design, may depend on your overall PPA (Power, performance and area) goals and the technology node you’re working on. However, generally speaking, it’s better to do downsizing first followed by leakage recovery. The reason being swapping the cells to higher Vt would again eat up most of the positive slack in your design, leaving minimal or perhaps no room for further downsizing. And there’s not much difference in the delay of X3 and let’s say X5 cells, it’s just that x5 will be able to drive a longer distance with a sharper (quicker) transition.


  1. Hold Fixing: The explanations needed here. You can fix hold by inserting buffer at common point or at the endpoint. Former approach would result in optimal number of buffers needed to fix hold timing, but may or may not impact setup timing. The latter approach would result in more number of buffers being inserted but the hold fixing rate would be more predictable and deterministic with possibility of setup degradation being minimal. Another approach could be downsizing or Vt swap, provided you have plenty of setup slack available along the paths failing hold time.


There could be some cases where the same path is both setup and hold critical. While such cases are rare, they do pop up in the design. Such cases need more careful study at very early stages in the design cycle, and many techniques have been proposed to fix timing on such paths, but it’s discussion would be beyond the scope of this post.


  1. Noise Fixing: Noise fixing should always be the last step in your Timing ECO cycle. Noise is very volatile, and designers cannot afford to fix noise at each and every step. Unless there’s something wrong systematically or there are tons of noise violations that designers may need to analyze which may require designers to re-visit their physical implementation, noise fixing should be done at the last. Any ECO changes- cell upsizes, Vt swaps, buffer insertions alters the timing windows and changes the noise picture. To decrease the number of iterations on fixing noise, it’s most pragmatic to do it at the last.


Last thing to note here is that a single iteration of timing ECOs can potentially degrade some other metric, however, only slightly. For example- if you are fixing setup violations by upsizing the cells you might see a slight degradation in your hold timing, and that’s expected. One might need to do multiple rounds of the above mentioned fixes, and as long as you’re converging in the right direction, timing ECOs are doing their job!


Now that you’ve fixed all timing violations, apparently meeting your Power, Performance and Area targets, you’re ready for tape-out!




Sankalp Semiconductor to present technical paper at CDNLive Bangalore

Sankalp Semiconductor a design service company offering comprehensive digital & mixed signal SoC solutions, will be presenting paper at CDNLive India 2018 during 6th & 7th September. The selected paper talks in depth on the “Automated Test Case Creation for Design Rule Deck Validation (DRDV)”. The paper will cover the following key points


  • PDK and its validation process
  • Rule deck validation flows
  • Automation that we have developed for rule deck verification.


When: From 3:00 PM to 3:30 PM on 6th September 2018
Where: Radisson Blu Hotel, Bengaluru, India



About Sankalp Semiconductor
Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including digital, analog, high-speed physical interface IP, Embedded Memory Compiler and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first pass silicon designs and engage with product engineering teams across the globe to design System-on-Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia.


Contact Information:
Sowmya Maskay
Sankalp Semiconductor
+91 9611024330 (Cell)




About CDNLive

CDNLive India 2018 brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems.

wafer fab location

Worldwide Location of Wafer Fabs – Interactive Map

Wafer fabs are the backbone of every electronic product. Every chip consists of a piece of silicon that is produced in a wafer fab. Wafer fabs play a key role in the customer, medical and automotive markets because the are they enabler of innovative technologies.


There are many wafer fabs globally and they have all different offering. The most known fab is TSMC and it’s by far the largest fab in terms of revenue and customer base.
In this article we are sharing a Google Map that we have created. The map shows the location of each wafer fab together with the fab offering and services (hint: click on the logo).

Should you have any comments or inputs drop us an email.