Monthly Archives: October 2018

PLDA and MegaChips announce a cooperation to design PCIe controllers and PCIe PHY IP on TSMC’s 16nm Process Technology

PLDA, the industry leader in PCI Express® IP solutions and MegaChips, a global semiconductor company specializing in ASIC Solution Services, today announced their collaboration to design a combined PCIe Controller IP and PHY IP solution. While the combination is currently targeting the TSMC 16nm process, the PCIe Controller/PHY solution will be easy to port to additional fabs and processes.


PLDA’s XpressRICH4 IP is a high performance, low latency, highly-configurable PCI Express Endpoint, Root port, Dual Port and Switch IP, compliant to the PCI Express Rev 4.0 specification and backwards-compatible to PCIe 3.1, PCIe 2.0 and PCIe 1.1. It is also available with a built-in DMA and an industry-standard AMBA AXI4 interconnect under its XpressRICH4-AXI version.


MegaChips is focused on concentrating their managing resources on R&D and new applications to create original technologies for value-added products. MegaChips is the only Japanese company ranked among the world top fabless IC suppliers and has developed numerous world-first technologies.


“We are seeing increasing interest in PCIe Controller/PHY combinations from third party IP suppliers because they give designers choices on ways to address their unique product design needs,” stated Arnaud Schleich, CEO of PLDA. Schleich added “Today’s announcement expands the available PCIe controller and PHY solutions for our valued, joint customer base.”


“The MegaChips PHY product is the best solution for the TSMC 16 nm process and ready to port to additional nodes and processes, making the combined PCIe 4.0 Contoller/PHY solution the most flexible on the market today,” said Kazunari Akaogi, General Manager of MegaChips.



PLDA XpressRICH4 and XpressRICH4-AXI IPs are available now from PLDA. The SerDes PHY IP is available now from MegaChips.



About PLDA

PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,800 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.



About MegaChips Corporation

MegaChips Corporation was established in 1990 as the first innovative fabless semiconductor company in Japan. MegaChips exploits expertise in analog, digital and MEMS technology and globally provides LSIs and solutions that are crucial for advancing technology innovation. .

Silicon Creations’ Fractional-N PLL Technology Leveraged at Israel’s Bar-Ilan University SoC Lab

Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), today announced that the SoC Lab at Israel’s Bar-Ilan University as part of the HiPer Consortium project has successfully integrated Silicon Creations’ LC and ring PLLs (phase lock loop) intellectual property (IP) in its SoC1 chip implemented in TSMC 28HPC process node. A second chip, SoC2, implemented in TSMC 16 FinFET process node and using Silicon Creations’ ring PLL IP is just months away from tape-out.


Silicon Creations produces a wide range of PLLs for most advanced process nodes. These include general-purpose Fractional-N PLLs, IoT PLLs with 32kHz RTC reference clock, Low-area Core voltage PLLs and Deskew PLLs for DDR interfaces as well as ultra-low jitter ring and LC-PLLs for demanding applications. The company’s PLLs are used in almost every vertical market and are an excellent choice for smart phones, battery-operated products, networking chips, energy-efficient and IoT chips, portable audio, set-top boxes, flat panel displays, high-performance computing, and mass storage.


“Israel has always been a very active region for us as a company. We have delivered both PLL and SerDes IP to Israeli customers for a wide variety of applications in very challenging process nodes including FinFET down to 7nm,” said Andrew Cole, vice president, Silicon Creations. “We are pleased to contribute our proven PLL technology to the SoC Lab at Bar-Ilan and support the university in developing the next generation of electronics.”


About Bar-Ilan’s SoC Lab

The SoC Lab, funded by the Ministry of Economy’s Magnet Program, was established to address multiple challenges of SoC design. SoC complexity is exponentially growing due to increasing demand for integration, compute capabilities, and efficiency. This complexity brings challenges in design, integration, verification and implementation. In addition, when time to market is a significant factor, an optimized generic flow is necessary.


For the first time, Israel has a scaled SoC design, implementation, and measurement laboratory that combines academic research with actual industry requirements. As a part of the HiPer consortium project, the Lab teams together with the industry partners to develop a generic and scalable SOC platform on which different research projects can be explored, implemented, and tested. The Lab’s vision is to help lower the “highly advanced technologies entry bar” for Israeli companies by providing a generic SoC Platform, and thus allowing them to focus on innovation by the reduction of overheads. More information about the HiPer consortium is available at



About Silicon Creations

Silicon Creations is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), SerDes and high-speed differential I/Os. Silicon Creations’ IP is in production from 7- to 180-nanometer process technologies. With a complete commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation. For more information, visit

ASIC Design – The Ultimate Guide

ASICs stands for Application Specific Integrated Circuits, and refer to semiconductor solutions design for a particular application, as opposed to other solutions like Field Programmable Gate Arrays (FPGAs) which can be programmed multiple times to perform a different functions. ASIC is also sometimes referred to as SoC (System on Chip).


The journey of designing an ASIC is a long winding road which takes you from a concept to a working silicon. Although the end product is typically extremely small (in mm2), the journey is quite interesting, full of challenges and trade-offs which the designers need to wrap their heads around to make the best engineering call. This post would try to elucidate different steps in the ASIC design flow starting from ASIC design specification to design tape-out for manufacturing in the foundry, and highlight important decisions and activities that each step entails. While the intricacies of each step might depend on the choice of EDA vendor, the design application and also the technology node, the sequence largely remains the same. Figure 1 shows the flow chart for the ASIC design flow.

ASIC design flow

Figure 1: ASIC Design Flow


ASIC Specification

The first step in ASIC design flow is defining the specifications of the product before we embark on designing it. This phase typically involves market surveys with potential customers to figure out the needs and talking to the technology experts to gauge the future trends. The latter is particularly important because ASIC design cycle may be anywhere between 6 months to 2 years. It is therefore important to foresee and predict what trends would be relevant 1-2 years down the line if one needs to sell their product to a wide audience.


This marketing research translates into high-level product specifications like top level functionality of what you intend to do with your ASIC, specific computation algorithm that you want to implement, clock frequencies that would make the product appealing to the customers, package type- Ball Grid Array (BGA) or CSP (Chip Scale Package) etc., power supply, communication protocols that will help interface with the external world, temperature range that you would want your product to work in.


Developing a thorough and correct specification usually sets a solid foundation for the ASIC design. The technical specifications need refinement of the technical requirements over time, but it’s important to cover the information in an unambiguous manner.


ASIC Architecture

After pruning the specifications, it’s now time to partition the entire ASIC or SOC’s functionality into multiple functional blocks. Architects like to brainstorm many possible options for the architecture and discuss their pros and cons while considering- performance implications, technical feasibility, and resource allocation in terms of both cost and time. A good architecture focuses on gleaning the best performance of the ASIC chip, while minimizing the hardware resources which directly helps in keeping the overall cost of the chip within the allocated budget. During this phase, architects define the relationship between various functional blocks and allocate time budget to each block. All these technical details are captured in an architecture document.



Micro architecture

Figure 2: Micro-architecture of Intel’s Haswell Processor. Image Courtesy: Real World Technologies


Once you have high level idea of all the functional blocks needed, it would be prudent to identify the critical modules and possibly brainstorm whether you need to re-use those IPs from previous projects, make necessary changes to the existing IPs or perhaps procure them from other parties.


The divide between hardware and software blocks is also a critical part of this phase of the ASIC design. Design is captured in a high level programming language like C++ or System C.


Logic Design and Verification


This step refers to the frontend part of the ASIC design flow and involves coding the data flow of each functional block in a hardware description language like Verilog, VHDL or System Verilog. The interactions between the functional blocks is also coded. Logic Design usually comprises of:


Combinational Logic: Combinational logic usually refers to Boolean combinatorial gates like the OR, AND, NAND, NOR etc. While these gates are simple, these can be combined to perform complex digital operations.


Sequential Elements: Sequential elements play a critical role in interfacing between different combinational logic clouds performing different functions by storing their output temporarily. These sequential elements like the flip-flops and the latches are also referred to as memory elements and are controlled by a synchronizing or a control signal referred to a clock. Both flip-flops and latches are bi-stable elements because they have 2 stable states: 0 or 1.


Finite State Machines (FSMs): These are higher abstraction of a sequential logic which can be implemented both in hardware and software. FSMs model response of a digital machine to a set of inputs to produce deterministic set of outputs, and serves as an important building block for logic designers.


Arithmetic Logic Blocks: Arithmetic computations form the heart of the computing logic, and usually is the bottleneck for performance in high performance CPU cores. Arithmetic computation includes addition, subtraction, multiplication and division. There are numerous possible implementations of these circuits which offer a trade-off between performance, area and power. Logic designers can choose one best suited for their application to optimize for one or more parameters.


Data-path Design: In addition to coding combinations of above elements, Hardware Description Languages (HDLs) can model data path design in an abstract manner like a programming language which can be interpreted by EDA tools correctly. These could be multiplexing, decoding, case statements etc.


Analog Design: In addition to digital logic, ASIC may have many analog components help in interfacing with the real world and may comprise of Temperature Sensors, Analog to Digital (ADC) and Digital to Analog Converters (DAC), and most importantly the clock generating unit the Phase Locked Loops (PLLs).


Example of a behavioral HDL code for 2:1 Multiplexer:




In parallel to logic design, verification team needs to develop a verification plan or both digital and analog logic components, and create testbench to be able to test the design for all possible corner cases to ensure correct functionality which needs to be consistent with the specification. Writing the RTL usually takes around 10-20% of the entire design cycle time, while Verification accounts for 80-90% of the time.


Physical Design

This refers to the backend design cycle. If there’s just one aspect that distinguishes the backend design from frontend design, then it would be- delay. Frontend design, while being cognizant of the logic delays and speed, largely ignores it for majority part of the RTL coding and verification. While, on the other hand, physical design sees real delay right from the very beginning.


Physical design flow is further sub-divided into the following:



Synthesis reads in the RTL code (.v or .sv files) along with physical libraries of the standard cells that may contain- delay information (.lib files), physical dimensions and metal layer information within the cell (.lef files) and other constraint files to convert the behavioral or dataflow code into real physical standard cell gates. Note that there are many possible implementations for 2:1 Multiplexer, and Synthesis is responsible to do an educated trade-off with performance, power and area to come up with the best implementation considering these constraints. As an example for the 2:1 Multiplexer, one possible implementation is below:



gate level

Figure 3: Gate level implementation of 2:1 Multiplexer



Floorplanning step formalizes and refines the floorplan that was first conjured up during the architecture planning step. In this step, the entire die area is divided into physical partitions, and their shapes are molded while keeping in mind the area requirements, the flow of top level data and control buses, possibility of any future growth. Pins and ports are assigned a rough location, which can further be refined depending on the Place and Route results.


ASIC floorplanning

Figure 4: Floorplanning the blocks relative to each other. Image Courtesy: Andrew Kahng, UCSD


It’s quite common for physical design engineers to work on more than 1 floorplan in parallel, and try to evaluate which one works best for overall design QoR (Quality of Results). This is usually the most critical step in physical design cycle, and requires multiple iterations. Any additional time spent here is worth it considering its long lasting implications on routing congestion, cell density, timing QoR and DRCs.


A robust power grid delivery- which addresses static and dynamic IR drop is also a critical function of the floorplanning step.



During placement, all standard cells are placed in legal locations on site rows. The aim of this step is to minimize the wire length, while ensuring optimal placement that will help faster timing convergence.


ASIC stanard cells

Figure 5: Standard Cells arranged on site rows. Image Courtesy: Andrew Kahng, UCSD


No real routes are laid during this step. Placement estimates routing through a step called Global Routing, where it estimates the total wire length and global route congestion. Many modern placement engines have the capability to take into account the switching activity from SAIF or VCD files, and try to optimize placement for achieving lower dynamic power.


ASIC placed design

Figure 6: Placed design. Image courtesy: Andrew Kahng, UCSD


Clock Tree Synthesis

Till now, clock network was ideal. During clock tree synthesis, clocks are propagated and the clock tree is synthesized using clock buffers. The major goals of this step is to achieve optimal clock latency while minimizing clock skew. There are many proposed algorithms to design an optimal clock tree- H Tree, Steiner Tree etc. In addition to this, one may choose Clock Tree Mesh, Multi-source Clock Tree Synthesis or traditional Single Point Clock Tree Synthesis which offer trade-offs for dynamic power, routing resources and OCV adjustment due to common clock path.



ASIC clock distribution

Figure 7: Typical H tree clock distribution. Image Courtesy: Research Gate


Clock being the signal with highest toggling frequency in the design, clock buffer tree accounts for over 75% of the dynamic power dissipated in an ASIC. Architecture may support clock gating to turn off idle parts of the chip to save dynamic power.


Detail Routing

With all instances placed and clocks routed, now it’s time to route the signal nets. Modern process supports 10-12 metal layer stack, with M0-M1 reserved for standard cell routing. The algorithm used for detail routing is usually a glorified maze router with added constraints to ensure faster run-times. The metal resources are divided into tracks which are the legal locations for metal routes. Aim of detail routing is to ensure minimum detours because these may have implications on timing, and to ensure minimum DRC (Design Rule Check) violations like opens, shorts etc. This step performs multiple search and repair loops (10-20) to keep the overall DRC count low.


Routed ASIC design

Figure 8: Routed Design. Image Courtesy: Andrew Kahng, UCSD


Physical and Timing Verification

While logic verification ensures correct functionality, physical verification ensures correct layout. There’s been an increase in Physical Verification checks which includes- DRC (Design Rule Checks), LVS (Layout versus Schematic), Electromigration, Electro-static discharge violations (ESD), Antenna violations, Pattern Match (PM) violations, Shorts, Opens, Floating nets etc. It is important to track these violations in parallel with the Place and Route flow to avoid any surprises just days before tape-out.


Timing Verification verifies that the chip runs at the specified frequency by ensuring setup and hold is met for all timing paths in the design.



Ferico ASIC

Figure 9: FRICO ASIC, 350 nm technology


ASIC design is a complex engineering problem that goes through a plethora of steps from concept to silicon. While some steps are more like art than engineering (like floorplanning), other some steps entail sound engineering trade-offs (like physical design and timing). With an increased demand for better performance and shrinking time to market, ASIC design flow would continue to get more intricate over the next decade. The core motivation and design philosophy, however, would remain the same.

Probing the Grey Matter

A new gold standard for electrical measurement in the emerging in vitro world of three dimensional models. That’s what Swiss medtech 3Brain has established by partnering with CSEM. Its Khíron chip enables fast, accurate intra-tissue measurement and continuous nutrient and oxygen supply through all tissue layers for the first time. And it is set to unlock the potential of next-generation cell culture models in disease modeling and preclinical studies.


Modeling systems have become a highly promising tool for understanding the mysteries of the brain, one of the biggest scientific challenges of the century. Over the last decade, three dimensional in vitrobiological models such as spheroids and brain organoids have emerged, proving to reliably mimic the microenvironment of living tissues and bridge the gap with in vivo animal models. As the spatial distribution of cells in tissue affects gene expression, signal transduction and several biological functions, this 3D approach enables far better disease modelling and preclinical pharmacokinetic studies than its 2D predecessor. Increasing use of this revolutionary technique has, however, revealed the limitations of existing methods for measuring the activity of neurons packed in a 3D environment.


Revolutionizing recording from complex 3D neuronal assemblies


The ‘z-dimension’ poses serious limits on optical measurements as well as on conventional planar micro electrode arrays (MEAs). Standard cell culture model measuring techniques can only monitor events on the surface of biological samples, thus missing the neuronal processing taking place in the three dimensions. 3Brain, the first company in the world to design and realize high resolution MEAs, has developed a solution that overcomes all these complex technological challenges. “With our new technology we aimed to get inside the tissue and replicate the right environment with continuous cell perfusion so that measurements are much more predictive of what will actually happen in clinical trials,” says Mauro Gandolfo, CEO of 3Brain.


3Brain, a CSEM spin-off, developed its new MEA chip in partnership within an Innosuisse project. Together, the partners have introduced several innovations. “These include microelectronic circuit design to interface a large neuronal network, post-CMOS MEMs processing to fabricate 3D electrodes and a packaging solution compatible with the culture of biological in vitro models,” explains Michel Despont, Vice-President and Head of CSEM’s microsystems program, whose team also carried out biological validation with relevant neuronal models. “CSEM’s ability to bring together this wide variety of competencies, combined with its long successful relationship with 3Brain, were instrumental in getting the chip for 3D brain tissue modeling to market.”


Improving disease understanding and drug development success


Named Khíron, the new application-specific integrated circuit (ASIC) provides a high density MEA specifically targeting intra-tissue measurement of a 3D structure in vitro models by integrating a micro-needle for each electrode for in vitro penetration of brain tissue. It also includes a microfluidic structure at the base of the chip for fluidic exchange even from the bottom layers, unlike most conventional MEA devices.


“The Khíron chip gives neuroscientists the tool they have been waiting for to solve their problems and acquire the information they want from 3D in vitro models” says Dr Gandolfo. “I think it will have a big impact in disease modeling for Alzheimer’s and Parkinson’s and also in the study of conditions like epilepsy and autism.”


3Brain will present Khíron at the SfN Society for Neuroscience annual meeting 2018 (3-7 Nov). The company will introduce its innovation to the market in 2019, initially targeting laboratories and universities interested in undertaking validation studies. It will then be integrated into the next generation of its products for the pharmaceutical and biotechnology sectors. 3Brain expects its new technology to double sales in two years.


Additional information

3Brain AG

Mauro Gandolfo CEO

Tel: +41 813227086



Michel Despont

VP, Head of microsystems

Tel. +41 32 7205478


Advanced Packaging Technologies are key for Semiconductor Innovation

“2017 was an unprecedented year for semiconductor industry”, comments Santosh Kumar, Director of Packaging, Assembly and Substrates at Yole Korea, part of Yole Développement (Yole). “The market grow by 21.6% year-to-year to reach record of almost US$412 billion”. Under this dynamic context, the advanced packaging industry is playing a key role, offering huge opportunities of innovation for the companies involved. According to Yole’s analyst, Santosh Kumar, the advanced packaging market should reach about US$ 39 billion in 2023…


The market research and strategy consulting company Yole, releases this month, its famous report, Status of the Advanced Packaging Industry. Santosh Kumar, with the help of the advanced packaging team at Yole, proposes today an impressive 2018 edition with key market trends, the description of technology evolution, a detailed analysis of the competitive landscape.


For the 1st time, this technology & market report includes a specific section dedicated to the advanced packaging technologies in the new semiconductor era. It offers a short term and long term outlook, with detailed roadmaps. It also details the impact of front-end scaling on advanced packaging. In addition Yole’s team points out the competitive landscape, with disruption and opportunities, detailed supply chain, production splits by manufacturers…



“This report is part of our key advanced packaging technology & market analyses,”asserts Emilie Jolivet, Director, Semiconductor & Software at Yole“Thanks to this report, we built a strong reputation and became step by step one of the major consulting companies in this area.”


To highlight results of this new advanced packaging report, Yole combines the release of this report with the relevant interview of a key advanced packaging player, Amkor Technology. OSATs clearly play a significant role in the evolution of the industry and Ron Huemoeller, Corporate Vice President, Head of WWRD & Technology Strategy and Christopher A. Chaney, IRC, Vice President, Investor Relations, both at Amkor Technology agreed to share their vision with @Micronews readers: More.


Between 2017 and 2023, the total packaging market’s revenue will grow at 5.2% CAGR[1]. In parallel, over the same period, the advanced packaging market will grow at 7% CAGR. On the other hand, the traditional packaging market will grow at a lower CAGR of 3.3%.


Of the different advanced packaging platforms, 3D TSV[2] and fan-out will grow at rates of 29% and 15%, respectively. Flip-chip, which constitutes the majority of the advanced packaging market, will grow at CAGR of almost 7%. Meanwhile, fan-in WLP will grow at a 7% CAGR from 2017 – 2023, mainly led by mobile.


“Advanced packages will continue their important role of addressing high-end logic and memory in computing and telecom, with further penetration in analog and RF in high-end consumer/mobile segments,” analyses Santosh Kumar from Yole. All of this while eyeing opportunities in the growing automotive and industrial segments.


What’s happened in 2017? According to Yole, two advanced packaging roadmaps are foreseen:


  • Scaling: going to sub10 nm nodes
  • And functional: staying above 20nm nodes.


In parallel, the semiconductor industry is developing products on both of them. Under this favorable context, advanced semiconductor packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost.


Both roadmaps hold more multi-die heterogeneous integration including SiP[3] and higher levels of package customization in the future. A variety of multi-die packaging is developing in both high and low end, for consumer, performance and specialized applications. Heterogeneous integration has created opportunities for both the substrate and WLP based SiP.


2017 also show the merger of 3 competitive areas that will continue to develop: PCB vs. substrate, substrate vs. Fan-Out and Fan-Out vs. 2.5D/3D


It will be difficult to repeat 2017 performances and Yole’s Semiconductor & Software team went further in its investigation this year again, to propose you today a comprehensive analysis of this evolution. Lot of questions are still pending and the Status of the Advanced Packaging industry will give you a deep understanding of the megatrends impacting this industry, the related business opportunities and technical innovations. A detailed description of this report is available on, advanced packaging reports section.



Some of these results will be presented at IMPACT 2018 Conference – TPCA SHOW 2018 this week. Ask for a meeting and meet Yole’s team!


Yole’s presentations proposed by Emilie Jolivet from Yole are:

  • “Impact of Artificial Intelligence on the semiconductor industry”, on 10/25, at 2:10 PM during the AI Forum, Impact.
  • Keynote: “Artificial intelligence and its challenge for the packaging and PCB industry”, on 10/25, at 4:11 PM at the TPCA Foresight Forum.
  • “5G’s impact on RF Front End SiP”, on October 26 at1:40 PM at the 5G Foru, Impact.



More information is available on

[1] CAGR : Compound Annual Growth Rate

[2] TSV : Through Silicon Via

[3] SiP : System-in-Package


Sankalp Semiconductor Expands its Design Centre in Hubli

Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, on 17th Oct inaugurated its design centre in Hubli. Shri Shivendra Gupta, Joint Commissioner of Income Tax, Shri Manish Kasodekar, Assistant Commissioner, Income Tax, and Shri Vivek G Pawar, CEO of Deshpande Foundation inaugurated the new Hubli design center. The company already has four design centres in India (Hubli, Kolkata, Ahmedabad and Bangalore). Sankalp’s new design centre is an extension of its center in Aryabhatta Tech Park, Navanagar.



“With the additional design centre space we plan to grow our team to 500 employees. Our Hubli centre, for more than a decade has been a centre of excellence for training and building specialized teams for chip design services. We are excited to support the growing needs of our global chip design customers.” said Nagaraj Azhakesan, COO, Sankalp Semiconductor.


Sankalp Semiconductor has executed multitude of complex digital and mixed signal SoC (System-On-Chip) projects for variety of its customers in Automotive, Consumer, Networking, Wireless, IoT, Medical, Foundry verticals.


Sankalp Semiconductor founded in 2005 with a focus to serve the semiconductor companies by primarily offering analog & mixed signal design services. Today, Sankalp with a team of 850+ engineering professionals has design centres in Hubli, Bangalore, Kolkata and Ahmedabad in India and Ottawa, Canada. The company provides unique advantage to its semiconductor customers by enabling them at any point of semiconductor services life cycle with the ability to provide end-to-end solutions.


About Sankalp Semiconductor


Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including digital, analog, high-speed physical interface IP, Embedded Memory Compiler and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partner to multiple Fortune 500 companies in the Automotive, Consumer Electronics, Industrial IoT and Medical electronics space. The company enables its customers achieve their time-to-market window by delivering first time right silicon designs and engage with product engineering teams across the globe to design System-on-Chip. Sankalp Semiconductor is based in Sunnyvale, California, with offices in USA, India, Canada, Germany and Malaysia.


Contact Information:

Eklovya Sharma

+91 9879048571