Monthly Archives: March 2019


Short Guide to Selecting IC Package

Semiconductor integrated circuits (ICs) are an essential component of every other modern technology which is why they have undergone some of the most extensive growth. Today, IC packaging offering is wide and deep with many kinds and types of semiconductor packaging technologies.  Your goal is, therefore, to select an IC package that suits perfectly to your ASIC, not over engineered – because it will increase your IC cost and not under engineered – because it could hurt your IC performance.


With the available variety, it can be difficult to determine what kind of IC package would best suit your needs and support your application ideally. You must take into consideration several different factors such as power, connectivity, application, costs, assembly capability, etc. Let’s further explore each of these various key elements.



Number of I/Os


This is an essential step when selecting your IC package. You want to lay down the specific groundwork dictating the number of input and output pins you need as well as the location of each pin on the target ASIC.


Tip: BGAs are ideal for high pin counts while it is recommended that you go for a QFN package or WLCSP if you are looking for a lower pin count.


BGA chip bottom view


Heat Management


Overtime, the physical size of an average semiconductor IC has gone down while its capabilities have become larger in capacity as well as much faster. As such, it is only understandable that it produces a significant amount of heat – which is why you have to consider the issue of heat management when deciding on your ASIC package. You want to make sure that you chip is operating within the optimum temperature range otherwise you might end up causing irreparable failures.


Tip: BGAs tend to be employ effective heat dissipation methods such as built in metal lid and conductive vias. QFN packages are smaller in size and use a metal exposed pads at the base of the package for this purpose are ideal for low power applications.


High Speed I/Os


You want to make sure that the interconnections in your package do not hamper down the quality of the input and output signals to your IC. You can, for example, choose whether you want bumping technology, which allow you to reach higher frequencies with lower inductance, or wire bonds, which enable you to use lower frequencies but will randomly variable inductance at each RF input and output. The layout of the package also dictates the integrity of the signal as it travels on the surface of the conductor and so the assembly of the board plays an important role in its transmission characteristics.


Tip: If you are looking for high frequency signals upwards of 5 GHz, then you should consider bumping technologies such as flip chip BGA, WLCSP or eWLB.


PCB Assembly


PCB assembly basically dictates how your IC is actually connected to the circuit board. You must give this some thought beforehand as there are multiple methods of doing so that you can choose from. You must also consider the fact that not every provider offers every method, so you might have to look for someone who does what you require. If you are opting for wafer level packaging, or bare die assembly, that has a small pitch (distance between the solder balls) then you will have to go to a service that can conduct this rather complex process and have adequate resources.




You must also think about the environment requirements that your IC be exposed to and the effect it may have on its longevity and performance. This will dictate the kind of material you use for the chip and the housing. You may have to use a ceramic or hermetic metal housing if you must protect it from moisture or chemical agents such as in the medical industry. Those involved in automotive must ensure that their packages can resist high temperatures, vibrations, and shocks derived from their environment.


Sankalp Semiconductor Expands International Operations in Japan

Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, today announced that it has appointed industry veteran Hisaya Keida in the key position as the Head of Japan. In this capacity, Hisaya Keida will manage sales operations and enable Sankalp’s presence in the key semiconductor and system markets.


Hisaya Keida has over 36 years of experience in the semiconductor space and a pioneer of fables ASIC business in Japan. Hisaya Keida was the CTO of Kawasaki Microelectronics, and responsible for all oversea (USA, Taiwan, India) operations and engineering before it was acquired by Megachips. His expertise lies in developing libraries, IOs, memories, analog mixed signal IPs in networking domains, process and manufacturing. Hisaya Keida holds Bachelor of Engineering degree from Waseda University in Tokyo Japan.


“Hisaya brings in rich semiconductor experience to Sankalp team. His induction will further enable our footprint in Japan,” said Samir Patel, CEO, Sankalp Semiconductor. “His proven leadership and track record will be instrumental in providing high quality semiconductor services and solutions needed from the Japan market.”


“I look forward to closely working with customers in Japan to provide Sankalp services and solutions. Sankalp is a unique company with comprehensive SoC and mixed signal design solutions & services capabilities,” said Hisaya Keida, Japan Head, Sankalp Semiconductor. “My focus will be to work closely with customers and engineering teams to delivery high quality solutions and services meeting customer schedules and expectations.”


Sankalp Semiconductor has executed multitude of complex digital and mixed signal SoC (System-on-Chip) projects for variety of its customers in Automotive, Consumer, Networking, Wireless, IoT, Medical, Foundry verticals. Sankalp Semiconductor was founded in 2005 with a focus to serve the semiconductor companies primarily offering analog & mixed signal design services. Today, Sankalp with a team of 950+ engineering professionals has design centers in Hubli, Bengaluru, Kolkata and Ahmedabad in India and Ottawa, Canada. The company provides unique advantage to its semiconductor customers by enabling them to engage at any point of semiconductor services life cycle with the ability to provide end-to-end solutions.



About Sankalp Semiconductor


Sankalp Semiconductor offers an integrated portfolio of services and solutions to its customers in key semiconductor domains including analog & mixed signal, digital, high-speed physical interface IP, Embedded Memory Compiler, IOs and EDA modelling. Sankalp Semiconductor is a preferred semiconductor design service partners to multiple Fortune 500 companies in the Automotive, Consumer, Networking, Wireless, IoT, Medical electronics and Foundry space. The company enables its customers to achieve their time-to-market window by delivering first time right silicon designs and engage with product engineering teams across the globe to design System-on-Chip. Sankalp Semiconductor is based in Palo Alto, California & Hubli, India with offices in USA, India, Canada, Germany, Malaysia and Japan.

SCALINX expansion continues with ASIC design center in Caen, France

SCALINX, industry recognized expert in new art of signal conversion technology, embedded in ASIC designs, has continued with its expansion plans and growth of its engineering staff in Caen design facility, which was opened in July 2018.


“The growth of the engineering staff in our design center Caen will allow SCALINX to accelerate the development efforts in terms of its innovative signal conversion ASICs road-map and help cement its position both in Europe and globally” said Hussein Fakhoury, CEO of SCALINX.


Highly professional and experienced design team which initially consisted of 5 engineers grew, since July 2018, to 15 ASIC design specialists.


SCALINX is looking forward to further growing the team and continuing to provide the ability augmenting the design support for its customers.


SCALINX, founded in 2015, is among the fastest growing and highly trusted companies in the Semiconductor Industry, designing signal conversion ASICs formed on its proprietary SCCORETM technology for Test & Measurement, Defense, Aerospace and Communications markets.


About SCCORETM technologySmart Conversion CORE technology uses proprietary wide-band Continuous-Time DS A/D Converter architecture facilitating solutions where bandwidth vs. resolution trade-offs are implemented in programmable digital circuity. This technology leads to significant power-efficiency improvement and BoM saving.


Read more about SCALINX here or here.


SoC Clock Domain Crossing – An Important Problem

Sometimes, when crossing clock domains, synchronizers are just not enough.


Imagine sending data serially over a single line and receiving it on the other side from the output of a common synchronizer as shown bellow.


Assuming one clock cycle is enough to recover from metastability under the given operating conditions, what seems to be the main problem is not the integrity of the signal – i.e. making sure it is not propagating metastability through the rest of the circuit – but rather the correctness of the data.


Let’s observe the waveform below. The red vertical lines represent the sampling point of the incoming signal. We see from the waveform that since sometimes we sample during a transition – in effect violating the setup-hold window – the output of the first sampling flop (marked “x“) goes metastable. This metastability does not propagate further into the circuit, it is effectively blocked by the second flop, but since the result of recovery from metastability is not certain (see previous post) the outcome might be a corrupt data.
In this specific example we see that net x goes metastable after sampling the 3rd bit but recovers correctly. In a later sampling, for the 6th bit we see that the recovered outcome is not correct and as a result the output data is wrong.


Another interesting case is when both the send clock and the receive clock are frequency locked but their phase might drift in time or the clock signals might experience occasional jitter.
In that case, a bit might “stretch” or “shrink” and can be accidentally sampled twice or not sampled at all.
The waveform below demonstrates the problem. Notice how bit 2, was stretched and sampled twice.


To sum up, never use a simple synchronizer structure to transfer information serially between clock domains, even if they are frequency locked. You might be in more trouble than you initially thought.


On the next post we will discuss how to solve this problem with ring buffers (sometimes mistakenly called FIFOs).



This is a guest post by Nir Dahan.

Number of 300mm Semiconductor Fabs Expected to Reach 121 in 2019

IC Insights recently released its Global Wafer Capacity 2019-2023 report that provides in-depth analyses and forecasts of IC industry capacity by wafer size, by process geometry, by region, and by product type through 2023. The newest edition of the Global Wafer Capacity report shows that 300mm wafers took over as the industry’s primary wafer size in terms of total surface area used in 2008. Furthermore, the number of 300mm wafer fabrication facilities in operation continues to increase. With nine new 300mm wafer fabs scheduled to open in 2019, the worldwide number of operational 300mm wafer fabs is expected to climb to 121 this year (Figure 1) and grow to a total of 138 fabs at the end of the forecast period.



Figure 1: Number of Semiconductor Fabs Processing 300mm Wafers


Some highlights regarding 300mm wafer fabs are shown below.

•    At the end of 2018, there were 112 production-class IC fabs utilizing 300mm wafers (there are R&D fabs and several high-volume fabs around the globe that make “non-IC” products using 300mm wafers, but these are not included in the count).

•    There are nine 300mm wafer fabs scheduled to open in 2019 (five of them located in China) following seven that opened in 2018.  Nine new fabs in 2019 would be the most opened in a single year since 12 were opened in 2007.  Another six are scheduled to open in 2020.  All of the new fabs coming in 2019 and 2020 will be for DRAM and flash memory or for foundry capacity.

•    The number of active volume-production 300mm fabs declined for the first time in 2013 when ProMOS closed two large fabs and two other fabs that were scheduled to open in 2013 where delayed until 2014.  The quantity of 300mm fabs has risen every year since.

•    By the end of 2023 there are expected to be 26 more fabs in operation than in 2018, bringing the total number of 300mm fabs used for IC production to 138.  For comparison, at the end of 2018 there were 150 volume-production 200mm wafer fabs in operation (the peak number of 200mm fabs was 210).


Report Details:  Global Wafer Capacity 2019-2023
IC Insights’ Global Wafer Capacity 2019-2023—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and device type through 2023. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities. Global Wafer Capacity 2019-2023 is priced at $4,890 for an individual user license.  A multi-user worldwide corporate license is available for $7,590.


To review additional information about IC Insights’ new and existing market research reports and services please visit our website:




More Information Contact

For more information regarding this Research Bulletin, please contact Bill McClean, President at IC Insights. Phone: +1-480-348-1133 email:



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