BrainChip Holdings Ltd (ASX: BRN), the leading AI EDGE company, today announced the availability of the Company’s Akida Neural Processing Core (“NPC”) as intellectual property available for licensing. This introduction marks a major development in the Company’s market presence.

The Akida NPC is now available to license as an IP block for incorporation into ASICs provided by semiconductor suppliers developing Artificial Intelligence enabled “Edge” devices. Applications at the edge include intelligent environmental controls, driver safety monitoring, vehicle safety and preventative maintenance, medical image classification, wearable health monitors, retail item recognition, access control, the industrial Internet-of-Things (IoT) and acoustic analysis.

The Akida NPC is a first-in-kind solution for ASIC integration and provides unprecedented performance, configurability, low power and small size. Validation of the Akida NPC is available with the Akida Development Environment (ADE) which fully simulates the Akida NPC size, performance and power and can be verified in a Field Programmable Gate Array.

The introduction of the Akida NPC marks a significant advancement in the Company’s market penetration strategy.

The need for a low power, high performance neural network to incorporate artificial intelligence into ASICs is a pressing concern for suppliers targeting edge applications and represents a large and growing opportunity for the Company.

The Company’s business model is multi-fold and includes:

• Akida NPC as an IP Block to semiconductor companies that develop ASICs which include a wide variety of additional functions.
• Akida as a device, a FlipChip 368 Ball Grid Array (BGA) through direct sales and global channel partners. The Akida device is a fully integrated neural network with no external CPU required to run the network targeted at edge applications.
• Akida as a USB dongle, for use in development environments and remote Cybersecurity applications through online sales and global channel partners.
• Akida on a reference board for the development of products and IP integration. The reference board can be used as a stand-alone neural network processor or in combination with a host computer and the ADE through a USB3.0 port.

The Akida NPC IP is modular, flexible, small and operates at unprecedented power levels depending on the processing demands of the application. The client’s entire neural network is running within the Akida neural fabric (this differs from so-called ‘accelerators’, which only perform fast multiplications and additions). Suppliers of smart sensors represent significant opportunities for early adopters to integrate the Akida NPC.

Linley Gwennap, principal analyst of The Linley Group, commented, “Spiking neural networks offer unique advantages over traditional AI models. By offering new levels of power efficiency and area efficiency, this approach is well suited to smart edge devices. An IP solution is essential for customers adding AI capability to high-volume SoC-based devices. Over the next few years, I expect a significant shift in AI processing from the data center to the edge.”

Peter van der Made, BrainChip Founder and CTO commented, “From the start, our goal has been to build a revolutionary integrated circuit which brings artificial intelligence to edge devices, and to provide our intellectual property on a licensed basis to the world. The small size, high performance, low power and reconfigurable nature of the Akida IP provides ASIC integrators with a unique solution for incorporation into their products over multiple generations and serves to improve their ASIC performance. I believe that we have the right solution at the right time. The market is ready for Artificial Intelligence in edge devices.”

About BrainChip Holdings Ltd (ASX: BRN)

BrainChip Holdings Ltd is a leading provider of low power, high performance edge AI technology using neuromorphic circuits, a type of artificial intelligence that is inspired by the biology of the human neuron. The Company’s revolutionary and proprietary new event-based spiking neural network technology can learn autonomously or execute pre-trained DNN entirely within the boundaries of the chip. The proprietary technology is fast, completely digital and consumes very low power. The Company provides hardware focused solutions that address high-performance requirements in sensory processing, gaming, financial technology, cybersecurity, ADAS, autonomous vehicles, and other advanced vision systems.

www.brainchipinc.com

San Jose, California – May 29, 2019. Mixel^® Inc., a leader in mixed-signal intellectual property (IP), and Teledyne Imaging, a leader in sensor, signal generation, and image processing, today announced that Mixel MIPI^® IP has been successfully integrated into Teledyne e2v Snappy 2-Megapixel and 5-Megapixel CMOS Image Sensor IC products.

The Snappy 2M CMOS image sensor combines full HD resolution in a 1 / 2.8 inch optical format thanks to an advanced 2.8μm low-noise global shutter, with features for fast and economic barcode identification and many industrial scanning applications.  The Snappy 5M CMOS image sensor builds on the Snappy 2M infrastructure, enabling fast, extended range scanning and includes powerful, unique, patented features and region of interest modes.

The Snappy family of sensors facilitate several applications, including embedded industrial imaging systems, drones/UAVs, IoT edge devices, intelligent surveillance cameras and augmented reality/virtual reality. In addition, both the Snappy 2M and 5M sensors have identical software and hardware requirements, enabling a complete range of scanners/cameras at different resolutions from a single system design effort.

Mixel provided Teledyne e2v with the MIPI D-PHY^SM and controller IP. Teledyne e2v achieved first-time silicon success and is now moving into high-volume production. The MIPI solution is comprised of two IP products delivered fully validated and integrated, namely: a MIPI D-PHY Transmitter and a MIPI CSI-2^SM Host Controller Core. The CSI-2 Controller IP is developed by Northwest Logic, an active participant in Mixel’s MIPI Central Ecosystem Partnership Program, which brings together best-of-class MIPI ecosystem stakeholders.

The D-PHY link can operate with 1 to 4 lanes, supporting 4.8Gbps aggregate data rate. It uses a clock-forwarded synchronous link that provides high noise immunity and high jitter tolerance.

The Mixel MIPI IP has been integrated in both of Teledyne e2v’s Snappy products and will be integrated in other new products as well.

“Mixel’s silicon-proven MIPI IP portfolio, wide coverage of process nodes, and outstanding IP metrics were important factors in our selection process. Our partnership with Mixel enabled us to achieve first-time silicon success and go into production with two different products in record time,” said Gareth Powell, Teledyne e2v’s Marketing Manager. “Mixel’s support during the integration phase was excellent and the bring-up went so smoothly we hardly needed any further support from Mixel,” he added.

Mixel’s MIPI PHY IPs have been silicon-proven at eight different nodes and eight foundries, giving Mixel the widest coverage in the industry.

“We are delighted to see Teledyne, a new Mixel customer, achieve first time success and go to production with multiple products, using the same Mixel IP,” said Ashraf Takla, Mixel’s President and CEO.  “It is also exciting to see Mixel IP integrated into Teledyne’s products in market segments addressing beyond-mobile applications such as embedded industrial imaging systems, drones/UAVs, and many others,” he added.

Mixel will be demonstrating many of its own and its customers’ products at MIPI Alliance’s MIPI DevCon Stuttgart developers conference in June.

About Mixel:

Mixel is a leading provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHY, M-PHY^®, C-PHY^SM, LVDS, and many dual mode PHY supporting multiple standards. Mixel was founded in 1998 and is headquartered in San Jose, CA, with global operation to support a worldwide customer base. For more information contact Mixel at info@mixel.com or visit www.mixel.com. You can also follow Mixel on LinkedIn, Twitter, Facebook, or YouTube.

About Northwest Logic:

Northwest Logic, founded in 1995 and located in Hillsboro, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance Memory Interface Solution (HBM2, GDDR6, DDR4/3, LPDDR4), Expresso Solution (PCI Express Gen5/4/3 & DMA cores and drivers, and MIPI Solution (MIPI CSI-2, MIPI DSI-2^SM). These solutions support a full range of platforms including ASICs and FPGAs. For additional information, visit www.nwlogic.com.

About Teledyne Imaging

Teledyne Imaging is a group of leading-edge technology companies aligned within the Teledyne brand. With unrivalled expertise across the electromagnetic spectrum and decades of experience, the group offers world-leading capabilities in sensing, signal generation and processing. The collective delivers innovative solutions to aerospace, defense, geospatial, machine and industrial vision, medical and life sciences, semiconductors and MEMs. For more information, visit www.teledyneimaging.com.

About MIPI Alliance

MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone manufactured today. Founded in 2003, the organization has over 300 member companies worldwide and 14 active working groups delivering specifications within the mobile ecosystem. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP tool providers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit www.mipi.org.

MIPI^® and MIPI M-PHY^® are registered trademarks owned by MIPI Alliance. MIPI CSI-2^SM, MIPI DSI^SM, MIPI DSI-2^SM, MIPI C-PHY^SM and MIPI D-PHY^SM are service marks of MIPI Alliance. Mixel^® and the Mixel logo are registered trademarks of Mixel, Inc.

Contacts

Mixel, Inc.
Justin Endo, 408-436-8500 x117
info@mixel.com
www.mixel.com

Northwest Logic
Joe Rodriguez, 503-533-5800 x310
info@nwlogic.com
www.nwlogic.com

Teledyne-e2v
Gareth Powell
Marketing Manager
gareth.powell@teledyne-e2v.com

Sofics bvba (www.sofics.com), a leading semiconductor integrated circuit IP provider announced that its technology to protect wireless antenna pads is now published as a patent by the European Patent Office. The clipping/scaling circuit is used to protect the Near Field Communication (NFC) antenna pads in an ultra-low power Bluetooth chip with ‘Touch-to-pair’ functionality. The first customer product, processed in TSMC 55nm technology, is running in mass production and is used for all kinds of home automation and IoT applications.

Sofics is a foundry independent semiconductor IP provider that has supported 60+ fabless companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. Recently, Sofics started with the development of circuit design solutions for increased robustness and reliability under the portfolio name PhyStar. The clipping circuit is the first such design that made it into a customer product. Other design circuits under development are automotive LIN and CAN transceivers and custom analog and digital I/Os.

Near Field Communication applications are ramping up because it can simplify aspects as diverse as communication, secure payments, user authentication, and retail loyalty programs for instance. Adding NFC functionality to an integrated circuit involves connecting the wireless interface pins to an antenna/coil. The voltage on those pads strongly depends on the distance between and alignment of transmit/read devices and the power of the transmitting device. Measures need to be taken to protect the wireless interface from excess voltages. The patented design from Sofics solves this issue by scaling the signal within the allowed normal operation and ESD design window.

“We are delighted that our patent application for our unique clipping technology was granted. This PhyStar circuit will reduce cost and risk for many IC companies working on NFC designs”, said Koen Verhaege, CEO of Sofics.

About Sofics – Sofics stands for “Solutions for ICs”. We are a foundry independent IP provider with a track record in on-chip robustness for ESD, EOS and EMC. Leveraging an extensive patent portfolio, more than 70 licensees, product proof in more than 50 processes, generates on average every day one new IC volume production release including Sofics IP.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced two extensions to its line of UDP/IP cores for lean Internet Protocol networking: an increase up to 32 channels for its existing 10G and 40G UDP/IP Hardware Protocol Stacks, and the upcoming release of a faster, 100G version of these IP cores.

The User Datagram Protocol (UDP) is part of the Internet Protocol (IP) suite of networking communication standards. It operates without the error resiliency of the Transmission Control Protocol (TCP), providing significantly faster networking with fewer hardware resources and less consumption of bandwidth. UDP/IP is thus well-suited to applications like live video broadcasting, where receiving most of the data packets on time matters more than receiving every single packet.

CAST has offered UDP/IP Hardware Stack cores since 2011, helping several dozen customers implement fast networking in a range of applications including industrial robots, satellite communications, wireless video transmission, scanner controllers, surveillance cameras, radar systems, and 3D surface measurement. These Hardware Stack cores operate independently, freeing a system’s processor from managing UDP functions to reduce design complexity and lower power consumption.

The new product line additions further expand the suitability of CAST’s UDP/IP solutions:

• Increased UDP channels—up to 32 transmit and 32 receive—enables breaking large data transmissions into smaller separate streams for parallel processing by slower systems, e.g. software UDP receivers, or the assignment of data from multiple sources to individual UDP streams for easier integration.
• While the current support for up to 40 gigabits per second Ethernet (40GbE) is more than adequate for many applications, the new core’s 100GbE capability will make the advantages of UDP/IP available to applications that must move more data faster.

About the UDP/IP Hardware Stack Cores

The increased UDP channels and 100G transmission capability make the features, performance, and silicon usage of CAST’s UDP/IP offerings comparable or superior to the few competing commercial cores. Features include:

• A complete UDP/IP Hardware Stack, including IPv4 support; Jumbo and Super Jumbo Frames; Unicast and Multicast; port filtering; checksums generation and validation; and optional Ethernet CRC validation.
• Support for related networking standards and functions including ARP with Cache; ICMP (ping reply); IGMP v3 (multicast); VLAN (IEEE 802.1Q); and a built-in DHCP client.
• Straightforward run-time configuration of operational factors such as the local MAC and IP addresses and multicast receive address, and extensive control functions such as enabling or disabling packet reception, checksum action, and DHCP fallback.
• Easy system integration, with flexible interfaces (AHB, AXI, Avalon, or Wishbone) and optional pre-integration with popular Ethernet MAC cores.
• Availability in synthesizable RTL for ASICs or optimized netlists for devices from Intel, Lattice, Microsemi, and Xilinx (see the product pages for sample implementation results).

“We engineered these cores to make it very cost- and resource-effective for customers to gain the benefits of UDP/IP, providing easy system integration and nearly negligible impact on silicon area or performance,” said Tony Sousek, director of CAST’s European development center. “These UDP/IP enhancements satisfy frequent customer request while also expanding the potential applications and systems that can benefit from UDP/IP networking.”

Availability and More Information

The 10G and 40G UDP/IP Hardware Stack Protocol cores are available now. The 100G UDP/IP Hardware Protocol Stack is undergoing extensive testing and will ship within two months. These UDP/IP stacks are part of the broad line of leading-edge and standards-based digital IP available from CAST, including compression engines and image processing functions; 8051 microcontrollers and low-power 32-bit BA2X™ processors; industry-leading automotive interfaces; a complete family of SoC security modules; and a variety of peripherals, interfaces, and other IP cores.

Learn more by visiting www.cast-inc.com.