Technology Trends
Process technology is progressing at a very fast pace and 16/14nm FinFET- based SOCs are available from various fabless companies. Significant investments in the development of advanced technology nodes are being made to ensure that future demands are met. This makes fab utilization of primary importance.
Recently we worked with a customer that had an urgent need to get a custom analog ASIC (application specific integrated circuit) developed in a very short time. The customer needed a completely working system in the first quarter of 2015. Working backwards from their system schedule they realized that they
Read MoreChip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.
Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries
Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?
Silicon dies which are placed on a wafer can also be described as many squares placed
Early on in Chip projects, yield is not taken very seriously. The common thinking goes – anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.
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Read MoreQFN package is probably the most successful package type today. Offering low price, excellent performance and small size, it is an ideal package for many applications.
QFN (quad-flat no-leads) is a plastic SMT package consisting of: a leadframe, single or multiple dies, wirebonds and a molding compound. The