Category Archives: Verification

SystemVerilog: Ultimate Guide

In the realm of hardware design and verification, SystemVerilog stands as a titan among languages, beckoning engineers and developers with its robust capabilities. Originating from the fusion of Verilog with hardware verification languages, SystemVerilog’s evolution has revolutionized the world of electronic design automation (EDA). An introduction to SystemVerilog not only

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The Ultimate Guide to ASIC Verification

Modern ASIC chips are highly complex and contain millions of transistors, thus, the likelihood of having an error somewhere in the chip during the design process is very high. The earlier the error is detected, the less it will cost. Therefore, ensuring the ASIC is bug free as early as

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Sankalp Semiconductor Announces Availability of Automated Analog Validation Services Environment – SAVE

Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, today at 55th DAC 2018 announced the availability of Sankalp Automated Validation Environment (SAVE). Sankalp will be demonstrating a video demo of the solution at its booth #2457. SAVE allows post-silicon validation of Analog

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Constrained Random Verification flow strategy

The explosive growth of cellular market has affected the semiconductor industry like never before. Product life cycle have moved to an accelerated track to meet time to market. In parallel, engineering teams are in a constant quest to add more functionality on a given die size with higher performance and less power

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Hierarchical Sequences in UVM

Rising design complexity is leading to near exponential increase in verification efforts. The industry has embraced verification reuse by adopting UVM, deploying VIPs and plugging block level env components at sub system or SoC level. According to a verification study conducted by Wilson research in 2012 (commissioned by Mentor) the engineers spend ~60%

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ASIC Verification: Build or Simulate?

Companies are using FPGAs for the variety of benefits they offer, including:

Running large sets of test data
Software development

The advantages of using FPGAs for verification include:

Smaller, less complex designs can be verified solely by building them in an FPGA
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