Category Archives: Verification

Sankalp Semiconductor Announces Availability of Automated Analog Validation Services Environment – SAVE

Sankalp Semiconductor, a design service company offering comprehensive digital & mixed signal SoC services and solutions, today at 55th DAC 2018 announced the availability of Sankalp Automated Validation Environment (SAVE). Sankalp will be demonstrating a video demo of the solution at its booth #2457. SAVE allows post-silicon validation of Analog

Read More

Constrained Random Verification flow strategy

The explosive growth of cellular market has affected the semiconductor industry like never before. Product life cycle have moved to an accelerated track to meet time to market. In parallel, engineering teams are in a constant quest to add more functionality on a given die size with higher performance and less power

Read More

Hierarchical Sequences in UVM

Rising design complexity is leading to near exponential increase in verification efforts. The industry has embraced verification reuse by adopting UVM, deploying VIPs and plugging block level env components at sub system or SoC level. According to a verification study conducted by Wilson research in 2012 (commissioned by Mentor) the engineers spend ~60%

Read More

ASIC Verification: Build or Simulate?

Companies are using FPGAs for the variety of benefits they offer, including:

Running large sets of test data
Software development

The advantages of using FPGAs for verification include:

Smaller, less complex designs can be verified solely by building them in an FPGA Read More

Moving towards Context Aware Verification (CAV)

The race between predictions vs. achievement of Moore’s law has had multi-fold impact on the semiconductor industry. Reuse has come to the rescue both from the design and verification viewpoint to help teams achieve added functionality on a given die size. This phenomenon lead to the proliferation of IP &

Read More

Evolution of the Test Bench

Nothing is permanent except change and need constantly guides innovation. Taking a holistic view with reference to a theme throws light on the evolution of the subject. In a pursuit to double the transistors periodically, the design representation has experienced a shift from transistors  à gates à RTL and now to synthesizable models. As

Read More