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CSEM has selected ID-Xplore™ to accelerate its analog design process

March 12, 2018, anysilicon

ID-Xplore™ was developed to give analog designers accurate, deterministic and correct-by-construction transistor sizing and design capabilities. “New technologies developed for ID-Xplore™ increase the designer’s ability to visualize performance sensitivity and understand the impact of design space tuning” explains Dr. Ramy Iskander, CEO of Intento Design. “CSEM’s decision to partner with us confirms the potential of our solution, as the Swiss R&D company is among the world leaders in the design of integrated circuits”.

 

We have been impressed by the speed and efficiency of ID-Xplore™ to capture designer intentions and to quickly explore a set of design solutions” says Alain-Serge Porret, VP Integrated and Wireless Systems, at CSEM. ”We appreciate the novel incremental design approach of ID-Xplore™, the facilitation of IP reuse and knowledge transfer between engineers to enable sharing of circuit design insights”.

 

ID-Xplore™ uses the OpenAccess database standard and is fully integrated within the Cadence design environment. The designer’s implicit & explicit knowledge is expressed as technology independent constraints. ID-Xplore™ enables seamless porting between technologies, and is fully compatible with the latest commercially available process design kits.