Low power design (CPF/UPF), Verilog RTL and constraint development and verification, DFT, logic/memory BIST, JTAG, ATPG, formal verification, synthesis/physical synthesis, floorplanning and prototyping (hierarchical and flat,) placement, routing, clock distribution (mesh and CTS,) routing, RC extraction, delay calculation, STA / timing closure, signal integrity, power analysis, DRC/LVS, DFM, package design, ATE interface, and failure analysis for a variety of chip architectures.