Reduce your IP verification effort by upto 75%

October 01, 2014, anysilicon

This is a guest post by Arrow Devices, that provides high-quality Design & Verification products and services for ASIC/SOC. 

Back in 2010 we saw the writing on the wall. Verification engineers for SOC and ASIC projects were spending a good deal of time on writing test-benches, writing test cases and debugging failures. Design verification had become a huge project in itself. According to some estimates, today about 70% of project effort is spent on verification activities. These activities are incidental to the final chip project deliverables and it’s almost a criminal offence for project managers and precious engineering resources to be focusing on these!

Chip managers agree that typically, about 30% of verification effort is spent in developing a test-bench, 25-30% effort is spent in writing test-cases and about 30% effort is spent in debugging failures with the rest of the effort spent in miscellaneous other activities. Recognizing these facts of a modern SOC development project, Arrow Devices set out to remedy the situation. Arrow Devices’ CheckMate range of verification IPs achieve this objective by providing not just BFMs but complete test-benches, coverage-suits and directed and constrained random test-suites as well as transaction level debugging tools.

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