The static timing analysis for the design is performed with respect to 4 distinct types of timing paths:
- In to Reg: The path from primary inputs to the chip to the input of a register.
- Reg to Reg: The path from output of a register to the input of another register.
- Reg to Out: The path from output of a register to the output pin of the chip.
- In to Out: The path from a primary input to the chip to the output of the chip.
STA engines check the timing status with respect to the above four categories of the timing paths with respect to setup, hold, maximum and minimum delay constraints.
