Silicon Creations Delivers 12.7G SERDES PMA for TSMC 40LP Process and PLL IP for TSMC 7nm Process

March 15, 2017, anysilicon

Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), today announced availability of several industry leading IPs for advanced TSMC processes including a 40LP 0.25Gb/s to 12.7Gb/s multiprotocol SerDes Physical Medium Attachment (PMA) and multiple 7nm PLL products. The PMA supports over 30 protocols including PCIe generations 1, 2 and 3, USB3.1-i/ii, SATA/SAS to 12Gb/s, CPRI rates 1 to 9, JESD204B 12.5G-LR and Ethernet 10G-KR, serving a broad range of market segments from networking to consumer products. The PLL products include a 5µW, 32kHz IoT PLL, low-jitter fractional frequency synthesizer, area optimized core voltage integer PLL, and high bandwidth deskew PLL.


Silicon Creations’ highly efficient architecture achieves RMS TIE jitter of less than 0.5% UI with minimal power consumption over the entire range of data rates. Achieving this level of performance with ring PLLs in a 40nm LP process may allow customers to reduce production costs and time to market, without sacrificing data bandwidth, power consumption, die area, or functionality.


In addition to the high-end SerDes development, many of Silicon Creations’ popular PLL products are now silicon proven in the new TSMC 7nm process, and in high volume production in both 10nm and 16nm (GL+, LL+, FFC). 12FFC PLLs are GDS ready now and will be silicon proven in late Q2 2017.


A new addition to the Silicon Creations PLL portfolio is the ultra-low power IoT design. One of the key requirements for IoT applications is low energy. Silicon Creations’ IoT PLL uses a “32kHz” reference clock enabling use of tiny, low power watch crystals. The whole PLL can use as little as 5µW in some processes. The IoT PLL can frequency lock within three clock cycles on warm starts to minimize the IoT chips’ energy needs. It is available in TSMC 7nm, 10nm, 16nm, 28nm, 40nm, and 180nm process nodes.


“We are proud to offer our IP on TSMC processes and be part of TSMC’s IP Alliance program,” said Andrew Cole, VP, Silicon Creations. “Having our advanced SerDes and PLL IP supported on industry leading foundry processes enables our customers to design more efficient and reliable chips.”


As a TSMC IP Alliance member, Silicon Creations’ extensive portfolio of PLL and high-speed I/O IPs have been qualified through the TSMC IP9000 program for a number of processes ranging from 180nm to 10nm. These IPs along with the TSMC 40nm LP SerDes PMA will be showcased at the upcoming TSMC Technology Symposium on March 15, 2017 held at the Santa Clara Convention Center in Santa Clara, California.


About Silicon Creations

Silicon Creations is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), chip-chip SerDes and high-speed differential I/Os. Silicon Creations’ IP is proven from 7nm to 180-nanometer process technologies. With a complete commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation. For more information, visit www.siliconcr.com.

Recent Stories