CXL is an aspiring new technology for high bandwidth devices like Accelerators, GPUs etc. In an era where there is growing need of High-Performance Computing (HPC), CXL offers high bandwidth and a low latency connectivity between Host (typically a CPU) and Devices like accelerators, memory expansion devices etc.
CXL leverages the existing PCIe 5.0 Physical Layer infrastructure and the PCIe alternate protocol negotiation process with some added advancements to support data transfer from multiple protocols.
CXL introduced a new component, Arbitrator and Multiplexer, to facilitate the use of legacy PCIe Physical layer. Arb-Mux dynamically multiplexes data coming from multiple protocols (CXL.IO and CXL.Cache-Mem) and routes it to the Physical Layer. This approach helps industry to transition and take advantage of the new capabilities enabled by CXL without having to make many updates in the Physical Layer, which has been one of the most complex components to design.
(Snippet showing placement of Arb-Mux in a CXL Stack)
Following are some salient features of the Arb – Mux:
VIRTUAL LINK STATE MACHINE (vLSM):
For a detailed description of all vLSM state transitions visit the CXL 2.0 base specification.
ARB – MUX LINK MANAGEMENT PACKETs (ALMP):
ALMP HANDSHAKEs:
Since PM and Active are virtualized states, following ALMP handshakes ensure Tx & Rx are in sync with the remote partner vLSM state.
(Snippet showing Entry to Active state)
(Snippet showing entry to L1 PM state)
(Snippet showing Status Exchange during LTSSM exit from Recovery)
ARBITRATION POLICY:
Arb – Mux provides arbitration (Tx) and Data steering (Rx) of the CXL.IO and CXL.Cache-Mem flits.
Arbitration policy is a weighted round robin with designated registers to program relative weights associated with CXL.IO or CXL.Cache-Mem, respectively. CXL 2.0 Memory Mapped Register contains the Arb – Mux Registers that defines variables to control this weightage.
Below is a pictorial representation showing how Arb – Mux Arbitrates the IO and Cache-Mem flits using the weighted round robin (WRR) method.
(Snippet showing Weighted Round Robin (WRR) Arbitration Policy)
We have 2 Buffers, CXL.IO flit Buffer and CXL.Cache-Mem flit Buffer. Consider a situation where both Buffers are full. As of now the weight set for CXL.IO is 4 and that of CXL.Cache-Mem is 2. Meaning 4 flits of CXL.IO will be followed by 2 flits of CXL.Cache – Mem.
With classical WRR approach, the 1st cycle will schedule first 3 flits from CXL.IO flit Buffer i.e., P1, P2 and P3. In the 2nd cycle, 1 flit from IO Buffer i.e., P4, since CXL.IO weight was 4, and the remaining 2 flits to be transmitted would be from Cache-Mem Buffer i.e., C1 and C2. Likewise, arbitration will occur for rest of the available flits in the buffers.
In case any one of the buffers is empty, Arb – Mux will automatically take care of sending flits only from that buffer which is non-empty.
VERIFICTION CHALLENGES:
Since, Arb – Mux is sandwiched between multiple link layers and an existing physical layer, a bug free implementation of this component is of huge responsibility.
Below are some challenges addressed by eInfochips during Arb – Mux Verification:
It is of utmost importance that these data transfer interface routes valid data to and from physical & link layer and vice-versa, during
The challenges are not only limited to the above listed items. We are in a field of surprises where we face multiple run time obstacles and are sometimes difficult to put into words.
DEALING with VERIFCATION BOTTLENECKS:
Dealing with above mentioned verification challenges and bottlenecks proficiently requires hard work, perseverance, and a brief level of technical expertise. Below listed attributes presents that how we as a team were able to address those challenges.
The above-mentioned pointers are just not limited to us, it can also be utilized by other teams, which can help them gear up their Arb – Mux and CXL Verification as a whole.
CONCLUSION
VLSI is an ever-enhancing industry. It is going to see similar enhancement in technology in the time that is to come. Since last two decades eInfochips has made sure to embrace all these new technologies and deliver effectively to client’s expectations by providing them concrete solutions and support. CXL is just another feather in the crown.
eInfochips provides a wide range of Verification solutions in the field of Semiconductor. Here at eInfochips, we provide end to end SoC and ASIC Design Services, IP/VIP Verification services across the entire connected product design flow, from test consulting and implementation to the end of life testing support, ensuring high product quality, operational excellence, and agility. To know more contact eInfochips.
About the Author
Vinit Sheth
Vinit Sheth works as an ASIC Design Verification Engineer at eInfochips. He has 3 years of working experience in the field of Verification and has worked on some complex protocols like CXL, PCIe, CCIX and USB.