Certus Semiconductor

Key attributes of our TSMC 55/65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a low-power HiZ state during power-down.  The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and optional internal 55K ohm pull-up or pull-down resistor.  ESD protection for two independent IO supplies and core power is constructed in an aggressive footprint.  A specialty output cell with matched throughput timings for pulse-width modulation (PWM) applications, along with 5V OTP programming, I2C & SVID open-drain and 3.3V & 5V analog cells complement the GPIO offering. The library is enriched with filler, corner and domain-break cells in digital and analog domains to allow for flexible pad ring construction.

1.0V-3.3V | 3.3V IO operation w two independent IO rails

Output enable / disable (HiZ when disabled)

Schmitt trigger receiver w 55KΩ selectable pull-up or pull-down resistor

ESD: 2KV HBM, 500V CDM, DDC, CEC and HPD compliant

I2C / SVID Open-Drain I/O:   Up to 3.3V external supply support

External resistor support of 1K-50K Ohm

Fail-safe

OTP Programming Cell is 6.6V compliant

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Silicon Proven

50um x 100um

A key attribute of the Certus 16nm & 12nm IO libraries is their ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.  The GPIO cell can be configured as input, output, open-source, or open-drain with an optional internal 50K ohm pull-up or pull-down resistor. Four selectable drive strengths are offered (25-235MHz @1.8V, 10pF) to optimize across SSO currents & power. The output driver exhibits 50Ω (±20%) termination across PVT to reduce reflections at higher operating frequencies.  ESD protection for VDDIO, VREF, and core VDD is constructed in an aggressive footprint. A 5V I2C / SMBUS open-drain (fail-safe) cell, 5V OTP programming gate cell and 1.8V & 3.3V analog cells are also available. This library features protection break cells to allow for separate grounds while maintaining ESD robustness.

Multi-voltage 1.8V / 3.3V switchable operation

4 selectable drive strengths (25-235MHz @1.8V, 10pF)

Independent power sequencing

50Ω (±20%) source termination across PVT

Schmitt trigger receiver w 55KΩ selectable pull-up or pull-down resistor

30um cell pitch (flip-chip)

2KV HBM, 500V CDM; 2KV IEC 61000-4-2 capable

Fail-safe

8-metal or 10-metal stack

Flip-chip package support (client configurable pads)

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Silicon Proven

30um x 50um

A key attribute of the Certus 22nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.  The GPIO cell set can be configured as input, output, open-source, or open-drain with an optional internal 60K ohm pull-up or pull-down resistor. ESD cells for IO & core power & ground are constructed in an aggressive footprint.  Digital cells for 25MHz, 75MHz, and 150MHz allow optimization across SSO currents & power. A 3.3V fail-safe I2C open-drain and 1.8V & 3.3V analog cells with ESD protection are also available. The library is enriched with feed-through, filler, transition and domain break cells to allow for flexible pad ring construction while maintaining ESD robustness.

Multi-voltage 1.8V / 3.3V switchable operation

25MHz, 75MHz, & 150MHz GPIO speed options

Schmitt trigger receiver

60KΩ selectable pull-up or pull-down resistor

2KV HBM, 500V CDM, and 2KV IEC 61000-4-2 capable

Up to 5V tolerant

Power-on sequence independence

Fail-Safe

Also DDC, CEC and HPD compliant

55um single inline wirebond pitch

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In Production

30um x 50um

The Certus TSMC 180 IO library is specifically tailored to address gaps in the native foundry IO offerings for this node.  It features a 1.2-1.8V GPIO with selectable dual drive strengths and optional internal 105KΩ pull-up or pull-down resistor. ESD protection cells for IO and core supplies are constructed in an efficient 60um x 80um footprint.  The analog suite includes 1.8V and 5V low-cap analog  / RF cells, a 7.5V OTP programming cell, and an ultra-low leakage / low capacitance 20-36V HV analog cell using only baseline CMOS processing layers. The library is enriched with filler, corner, domain break, and secondary CDM cells to allow for flexible segment construction.

GPIO 1.2V-1.8V operation (IO & core)

Selectable 15pF | 30pF load support options at 50MHz

Schmitt trigger receiver w 105KΩ selectable pull-up or pull-down resistor

ESD: 2KV HBM, 500V CDM

Analog 1.8V and 5V tolerant options

20-36V High-voltage, low leakage cell

Low capacitance / RF

OTP Programming Cell 7.5V tolerant supply gating cell

Flip-chip using client configurable pads

Secondary CDM cells

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Silicon Proven

60um x 80um

The GPIO pad set provides basic digital IO cells and the associated IO power, core digital power, and ground cells with built-in ESD circuits. This pad set also has macro blocks implementing LVDS TX and LVDS RX circuits. There is a stand-alone Analog/RF cell that passes-through an ESD protected analog/RF signal. Current footprints and formats comply with minimum dimensions for Global Foundries packaging requirements. The IO Libraries are exceptionally reliable from an ESD perspective, and are in fact capable of exceeding 4kV HBM and 800V CDM, however such levels of ESD qualification depend more on final padring construction, as opposed to achieving a standard 2kV HBM and 500V CDM qual.

200MHz operation for 10pF Loads 150MHz operation for 15pF Loads

Output enable / disable (HiZ when disabled)

Selectable pull-up or down termination resistors

Dynamically Selectable drive strength: 12mA and 24m

Complies with JEDEC JESD 8-5 LVCMOS Specs

2.5V and 3.3V variants available

HBM 2000-4000V CDM 500-800V MM 200V

LVDS TX and LVDS RX Features 1.5Gb Data rates Self-Biased, no reference blocks needed

Complies with ANSI/TIA/EIA-644-A

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Silicon Proven

45um x 200um