FrenusTech

India

Our Focus: End to End VLSI Design Services and Embedded Systems.

We provide Solutions / Engineering Talent: To build Intellectual Properties (IPs) and System On Chips (SOC) involving both Digital & Analog design for Accelerator based SOCs, Consumer Electronics, IOTs, Automotive and Aerospace.

Our core leadership team brings in vast expertise from various domains of VLSI design. We have successfully delivered more than 8-IP s and 4-SoC to our customers in full ownership mode.

Services

Digital Verification

IP Verification & Validation

  • Test feature extraction and test plan creation
  • Functional coverage matrix to get maximum cross-functional verification
  • Complete Verification Environment built up from scratch

 

Multicore SoC Verification

  • SoC level verification and expertise in System Architecture to take up SoC verification
  • Expertise in various processors from RISC based, DSP & Crypto processor cores
  • Experience in various complex Protocols and Standards such as USB, Ethernet, PCIE, Wireless, DO-254
  • Experience in Power architecture and UPF flow simulation

Physical Design

Physical Design, Verification and Sign Off

  • We have expertise in taking full ownership of RTL to GDS for Block Level or Top Level.
  • We have three successful Tape Outs with full ownership where we built the entire Back End flow and delivered from Netlist to GDSII. One project was delivered in turnkey mode for a China client.
  • Our Physical Design team has expertise in technology process nodes from 7nm FINFETs to 350nm BCDMOS.

 

Synthesis

  • Setting up the synthesis flow
  • Verifying constraints
  • Different logic/timing/power optimization techniques

 

Static Timing Analysis (STA)

  • Setting up the STA flow
  • Develop timing constraints and exceptions
  • Timing Analysis for multi modes & multi corners
  • Timing ECOs using TSO or manual for timing critical paths

 

Physical Design & Verification

  • Setting up the Physical Design Flow
  • Floor Planning at Top Level & Block Level
  • Power Planning at Top Level & Block Level
  • Placement and optimization
  • Clock Tree Synthesis (CTS)
  • Routing and optimization

 

Logic Equivalence Check (LEC)

  • Setting up the LEC flow for both functional and CLP
  • Develop constraints
  • Analysis & Debug

Sign Off

  • Power Integrity (Power EM and IR-Drop)
  • Signal Integrity (Sig EM, IR-Drop and Noise)
  • Physical Verification (DRC, LVS, ERC, Customer Specific Checks)

DFT – Design for Testability

  • DFT Implementation – Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression
  • Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
  • Automatic Test Pattern Generation (ATPG), ATPG verification.
  • DFT simulations and timing for SCAN, Boundary SCAN, MBIST & LBIST modes.

Analog, Mixed Signal, RF & Power Management

Analog, Mixed Signal and RF – Design, Verification & Layout

  • Analog Circuit Design
  • Analog Design Verification – Simulation based
  • Analog and Mixed Signal Modelling (AMS-Modelling)
  • Analog and Mixed Signal Verification (AMS-Verification)
  • Analog and Digital Co-Simulation
  • Layout Design – Analog, Mixed Signal, RF, Custom-Digital etc.
  • Post Layout – Extraction, Simulation and Layout/Circuit fixes.
  • Physical Verification (DRC, LVS, ERC, Latch-up, Soft-Conn, DFM etc.)

Tech Foundation IPs (Standard Cell, Memory & IO)

Memory – Design, Characterization, Validation and Layout for all below types:

  • SRAM – Memory Instances
  • SRAM – Memory Compilers
  • Cache Memories

 

Standard Cell Library – Design, Layout, Char, Lib-QC, LEF, Tech-LEF and PD-Validation for:

  • High Performance Libraries – Multi-VT, Multi-Channel (10-Track Libs and above)
  • High Density Libraries – Multi-VT, Multi-Channel (8 and 9 Track Libs)
  • Ultra High Density Libraries – Multi-VT, Multi-Channel (6, 7 and 7.5 -Track Libs)

Embedded Systems

  • Porting from 8-bit/16-bit controllers to 32-bit or 64-bit microprocessors and Integrations
  • Development of protocol stacks, system interface drivers, memory devices
  • System and Product Validations, Connectivity compliance
  • HBA and SSD firmware (SAS/SATA device controller firmware)
  • ACPI Firmware, Server BIOS validations
  • Touch controller and Application processor communication protocol firmware
  • Firmware and on-board diagnostics
  • Platform migrations – OS Porting/Customization/Enhancement Services
  • Feature enhancements
  • Development of Board Support Packages & BSP enhancements
  • Device Drivers for various reference designs and for new processors/Board
  • Porting of Applications onto different operating systems

IP Cores

Hardware Accelerator for Crypto currencies

As we go deeper into cryptocurrency and mining, the mining hardware efficiency is the key to success

 

The mining is becoming increasingly challenging and competitive and the real ROI comes from faster and efficient

hashing

 

This is possible through custom made designs and modifications in algorithm

 

We have a very good design that can compete with existing world leaders in bitcoin and litecoin mining

 

The designs are widely used in security algorithms apart from crypto-currencies, especially SHA256 algorithm (backbone of bitcoin)

Interface IPs: SERDES, DDR, GPIO, LVDS

Low-Power High-Speed CML SERDES – in TSMC 40nm

  • CML SerDes is 55% faster than CMOS implementation.
  • Nominal data-rate: 12.67 Gb/s & Throughput: 1.05 GByte/s at 14.3mW.

DDR PHY IPs: in TSMC 40nm

  • DDR 3
  • LPDDR2

Bi-Directional GPIO in TSMC 40nm CMOS

  • Supply : 2.5V, Core supply: 1.1V single ended, Output Swing: 2.5V
  • Data rate : 2Gbps, Clock frequency :1GHz

 

2 Gbps LVDS Transceiver (Tx & Rx)  in TSMC 40nm CMOS

  • I/O Supply : 2.5V, Core Supply 1.1V single ended

TX Specifications

  • Output Differential voltage : 200mV – 400mV
  • Output offset voltage :0.925V – 1.275V, Output Impedance : 100 ohms
  • Tskew1 : 45ps, Differential signal rise and fall time : 50ps (Min) & 200ps(max)

RX Specifications

  • Clock buffer speed : 1GHz (max)
  • Receiver differential input impedance : 80 ~ 120 Ohms
  • Common mode voltage range : 0 ~ 2.4V (for 100mV VID)

PLLs– Phase Lock Loop

Type – 2 Charge Pump based 1 GHz  to 22 GHz PLL in 22nm FDSOI, Supply: 1.2V

  • Settling time less than 1us, Phase noise -108 dBc/Hz at 1MHz,
  • Duty Cycle 50% ±5%, Reference frequency 64MHz

 

Type -2 Charge Pump based  PLLs in TSMC- 40nm, Supply 1.2V

2.4GHz PLL

  • Settling time less than 2us, Jitter less than 4ps, Phase noise -77dBc/Hz at 1MHz
  • Duty Cycle 50% ±5%, Reference frequency 80MHz,
  • Overall power consumption 2.8mW

800MHz PLL

  • Settling time less than 4us, Jitter less than 6ps, Phase noise -95dBc/Hz at 1MHz
  • Duty Cycle 50% ±5%, Reference frequency 25MHz
  • Overall power consumption 1.1mW

Data Converters: ADCs and DACs

12-bit 320 MSPS Pipeline ADC in GF22 FDSOI, Supply: 0.9V

  • Resolution :12-bits with 2.5bits (CDS) + 4 * (2.5bit) (with shared op amp) + 2bit flash
  • ENOB – 11.2 bits, +/- 0.5 LSB DNL, +/- 1.2 LSB INL
  • Signal Bandwidth – 80MHz, Power consumption – 30mW

 

12-bit 320 MSPS Current Steering DAC in GF22 FDSOI,

  • Resolution : 7bit Binary and 5bit Thermo
  • ENOB – 11 bits, Supply: Digital-0.9V , Ananlog-1.2V
  • Signal Bandwidth – 40MHz, Total Current– 2mA

 

11-bit 20MSPS IQ –SAR ADC in GF22 FDSOI

  • For Low-power IoT applications
  • On-Chip Voltage reference with Internal Bandgap and Biasing system
  • Segmented DAC with VCM switching technique
  • ENOB 10.2 bits for 5MHz input signal

Power Management IPs

GF22nm FDSOI, with LD-MOS Transistors

 

250mA, DC-DC Buck converter

  • Input Voltage 2.3V to 5V, Output Voltage : 0.8V to 1.6V
  • Efficiency: 86% full load, Output ripple ~3mV (output – 1.6V)
  • Load current 200mA max, Output voltage programmable by 5bits.
  • Synchronous and Asynchronous modes of operation.
  • Switching frequency – 6.75Mhz

 

Negative Charge pump to provide bulk bias voltage for FDSOI transistors.

  • Input Voltage 2.3V to 5V, Output Voltage max : -3.6V
  • Output Voltage Programmable from -500mV to – 3.6V in 16 steps (4-bits)
  • Output ripple ~1mV. [connected with load]
  • Load current 100uA max, Quiescent current : 70uA
  • Settling time 100us, Off state leakage < 20nA

 

Regulated Positive Charge pump to provide bulk bias voltage for FDSOI transistors.

    • Input Voltage 2.3V to 5V, Output Voltage max : 3.6V
    • Output Voltage Programmable from 500mV to 3.6 V in 16steps (4 bit prog)
    • Output ripple ~1mV, Load current 100uA max, Quiescent current : 40uA
    • Settling time 100us, Off state leakage < 20nA