FrenusTech

IP Verification & Validation

• Test feature extraction and test plan creation
• Functional coverage matrix to get maximum cross-functional verification
• Complete Verification Environment built up from scratch

Multicore SoC Verification

• SoC level verification and expertise in System Architecture to take up SoC verification
• Expertise in various processors from RISC based, DSP & Crypto processor cores
• Experience in various complex Protocols and Standards such as USB, Ethernet, PCIE, Wireless, DO-254
• Experience in Power architecture and UPF flow simulation

Physical Design, Verification and Sign Off

• We have expertise in taking full ownership of RTL to GDS for Block Level or Top Level.
• We have three successful Tape Outs with full ownership where we built the entire Back End flow and delivered from Netlist to GDSII. One project was delivered in turnkey mode for a China client.
• Our Physical Design team has expertise in technology process nodes from 7nm FINFETs to 350nm BCDMOS.

Synthesis

• Setting up the synthesis flow
• Verifying constraints
• Different logic/timing/power optimization techniques

Static Timing Analysis (STA)

• Setting up the STA flow
• Develop timing constraints and exceptions
• Timing Analysis for multi modes & multi corners
• Timing ECOs using TSO or manual for timing critical paths

Physical Design & Verification

• Setting up the Physical Design Flow
• Floor Planning at Top Level & Block Level
• Power Planning at Top Level & Block Level
• Placement and optimization
• Clock Tree Synthesis (CTS)
• Routing and optimization

Logic Equivalence Check (LEC)

• Setting up the LEC flow for both functional and CLP
• Develop constraints
• Analysis & Debug

Sign Off

• Power Integrity (Power EM and IR-Drop)
• Signal Integrity (Sig EM, IR-Drop and Noise)
• Physical Verification (DRC, LVS, ERC, Customer Specific Checks)

• DFT Implementation – Test Pin-Muxing, SCAN Insertion, LBIST Insertion, Compression
• Logic Insertion, Boundary Scan Insertion, Memory BIST insertion and IOs.
• Automatic Test Pattern Generation (ATPG), ATPG verification.
• DFT simulations and timing for SCAN, Boundary SCAN, MBIST & LBIST modes.

Analog, Mixed Signal and RF – Design, Verification & Layout

• Analog Circuit Design
• Analog Design Verification – Simulation based
• Analog and Mixed Signal Modelling (AMS-Modelling)
• Analog and Mixed Signal Verification (AMS-Verification)
• Analog and Digital Co-Simulation
• Layout Design – Analog, Mixed Signal, RF, Custom-Digital etc.
• Post Layout – Extraction, Simulation and Layout/Circuit fixes.
• Physical Verification (DRC, LVS, ERC, Latch-up, Soft-Conn, DFM etc.)

Memory – Design, Characterization, Validation and Layout for all below types:

• SRAM – Memory Instances
• SRAM – Memory Compilers
• Cache Memories

Standard Cell Library – Design, Layout, Char, Lib-QC, LEF, Tech-LEF and PD-Validation for:

• High Performance Libraries – Multi-VT, Multi-Channel (10-Track Libs and above)
• High Density Libraries – Multi-VT, Multi-Channel (8 and 9 Track Libs)
• Ultra High Density Libraries – Multi-VT, Multi-Channel (6, 7 and 7.5 -Track Libs)

• Porting from 8-bit/16-bit controllers to 32-bit or 64-bit microprocessors and Integrations
• Development of protocol stacks, system interface drivers, memory devices
• System and Product Validations, Connectivity compliance
• HBA and SSD firmware (SAS/SATA device controller firmware)
• ACPI Firmware, Server BIOS validations
• Touch controller and Application processor communication protocol firmware
• Firmware and on-board diagnostics
• Platform migrations – OS Porting/Customization/Enhancement Services
• Feature enhancements
• Development of Board Support Packages & BSP enhancements
• Device Drivers for various reference designs and for new processors/Board
• Porting of Applications onto different operating systems