JVD Analog ASIC Semiconductors


All JVD ASICs are custom hand designed by a team of more than 30 analog IC engineers whose average experience is >35 years. We do not use analog cell libraries. Anyone who does is putting your design at risk. Do the research. Cells waste space in chip layout. They are rarely the ideal electrical solution for critical, precision analog requirements. They restrict the designer’s wafer fabrication process choices, forcing performance tradeoffs that can undermine the chip’s success.


All JVD ASICs are designed in the US and all silicon in produced by wafer fabs in the US unless specifically requested by the customer. All wafers are 100% electrically tested before packaging and again 100% tested prior to shipment.


ASICs should not carry a cost penalty over off-the-shelf standard products. Most customers qualify for a 100% rebate of all the development and tooling costs.  Customer’s volumes range from 15K/ yr to 15M/yr