Mn_nH

Korea

We are silicon IP provider specialized for video processing. We are made up of over 15 years experienced ASIC design engineers and have made multimedia SOC, ISP and video IP cores.

 

Several customers use our IP and many chips designed by us. We will provide you with high performance compact IP and professional support.

IP Cores

HEVC Codec IP

H.265 Encoder / Decoder IP up to 8K 30fps

H.264 Codec IP

H.264 Encoder / Decoder IP up to 8K 30fps

 

IP Specification
• H.264 Encoder High profile
• H.264 Decoder : Self encoded stream decoder
• ASIC level encoding efficiency
• Zero delay optimized : Under 3ms up to 8K encoding
• Max resolution : YUV 4:2:0, Expandable up to 8K
• Max perfomance
1920×1088 60 fps UltraScale+ Kintex
4096×2160 60 fps UltraScale+ Virtex
8196×4320 60 fps ASIC
• Compact Logic Size
• Optimized system bus bandwidth

Encoding Tools
• Macro-block 16×16 / 8×8 / 4×4 all estimation
• Intra prediction 0 ~ 8 all support
• Wide motion search range (+-96, +-48) for Moving application
• 1/4 sub-pel motion search
• IPPP 1 reference frame
• Deblock filtering
• Multi-slice encoding support
• De-quant for ROI image enhancement

JPEG Codec IP

JPEG Encoder / Decoder IP

 

IP Specification
• JPEG Base Profile support
• Format
Decoder : YUV444 / YUV422 / YUV420 8-bit support
Encoder : YUV422 / YUV420 8-bit support
• Resolution
up to 4240×2832 (Expandable with multi core processing)
• Performance (Decoder estimated)
1-core 1920×1080 6~7fps @ 120Mhz
9-core 1920×1080 60fps @ 120Mhz
• FPGA Utilization
1-core : Xilinx Logic Cell 12,558 (7.74% of 160T)
9-core : Xilinx Logic Cell 113,025 (70% of 160T)
• Mass production for several ASIC process as 90nm, 65nm, 40nm

Frame Buffer Compression IP

Lossless frame buffer compression IP

 

IP Specification
• Lossless compression for bus bandwidth reduction
• Typical 45% (min 25% ~ max 75%) bandwidth reduction
• Flexible specification with scalable and customisable design

✓ YUV420 1080P 30fps at 120Mhz : compression IP 53K gate count decompression IP 27K gate count
✓ YUV420 2160P 30fps at 240Mhz : compression IP 84K gate count decompression IP 54K gate count
✓ Bayer 14bit 1080P 30fps at 120Mhz : compression IP 92K gate count decompression IP 47K gate count
✓ Bayer 14bit 2160P 30fps at 240Mhz : compression IP 147K gate count decompression IP 94K gate count

360 Stitching IP

Multiple camera image stitching IP

 

Specification
• 1 Channel : Lens distortion correction
• Up to 24 multi channel image stitching for 360 degree panoramic image
• YUV 420 8-bit and any resolution format support
• 2D or Stereo alignment for 3D 360
• Equirectangular / Top Bottom 3D format output
• Filtering and smoothing for seamless image
• Blending ISP difference for HDR between multiple source channels
• Random rotation and warping at each pixel for any camera rig support
• Stitching optimized smart cache controller
• 3840×1920 60 fps at 425 Mhz for ASIC
3840×1920 60 fps at 120 Mhz for FPGA
• Scalable and expandable design for performance upgrade
• Bandwidth reduction On the fly with MnHEVC / MnHTC encoder IP
• Application : Drone / ADAS / VR Camera / Robot / Military / Boring Cam

Delivery
• Technical documentation
• Stitching tuning S/W tool
• Firmware to control H/W IP
• Verilog RTL source code and testbench

SWIR / NIR ISP IP

Short wave IR ISP IP

AXI chip to chip IP

AXI chip to chip between ASIC or FPGA