Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software, and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world.

Open-Silicon provides flexible model to engage  at any stage of the design and delivers fully tested silicon packaged parts to customers.

–       Spec Handoff to Chip

–       RTL Handoff to Chip

–       Netlist Handoff to Chip

–       GDS2 Handoff to Chip


ASIC and SoC Design

Derivatives and Spec Handoff (Turnkey) Designs

With spec handoff designs, Open-Silicon leverages it’s deep experience in Networking, Telecom, Storage, and Computing to take the lead in defining the SoC architecture and system design.

Spec Handoff

The starting point for a custom SoC can be an idea, concept, block diagram or specification.  Open-Silicon’s technical solutions managers will work with the customer to review the available industry expertise and technology and select the best solution for each program.  Then, Open-Silicon’s experienced systems engineers will work with customer to develop a full product plan including a microarchitecture specification suitable for RTL design and design verification.  From that point, Open-Silicon’s program manager will provide a single point of ownership for all actions, managing the project through Open-Silicon’s ASICView program management software.

Open-Silicon’s teams have strong vertical expertise that enables them to make the right decisions for customers to minimize the amount of customer engineering needed to fully develop a new semiconductor product. From a detailed design flow and process, and a commitment to complete documentation, to a rigorous system of checklists, customer’s can trust Open-Silicon to put quality first and execute to their satisfaction.

ASIC Design

Open-Silicon’s roots are in traditional ASIC design, including both RTL and Netlist handoffs.  Open-Silicon continues to expand its ASIC offerings, including more IP partners, optimal foundry technology choice, and in-house technology solutions to design the best possible custom silicon.

Disciplined Methodology

Open-Silicon’s design engineering teams are experts in handling complex ASIC designs, with the experience of over 10 20 million gate designs under our belts. Our disciplined approach, combines active feedback to customers throughout the design process and ensures that programs are executed to a predictable design timetable. Our innovative design methodology, combined with our deep design expertise and experience in the selection, qualification and integration of third party IP, enables the consistent delivery of reliable silicon.

Early analysis of each customer’s design by our engineering team, including running Open-Silicon’s in-house developed DesignScanner software, allows us to identify and resolve technical challenges even before the design is completed. Our rigorous and rigid design methodology then reduces any chances of design escapes, allowing us to deliver an industry-leading level of first-time silicon success.  Over two thirds of Open-Silicon’s new design starts come from repeat customers.

Prototyping and Validation


Open-Silicon offers full system prototyping, hardware board design, and software development solutions to help our customers complete their semiconductor product development. System prototyping solutions are based upon FPGA-based platforms for logic emulation, often combined with  evaluation boards for IP such as high-speed interfaces or high-performance processors.

Offering a prototyping solution provides customers with a one-stop-shop with reliable execution throughout the product design and manufacturing process. Open-Silicon’s prototyping solutions is an executable, cost-effective representation of an SoC, board and I/Os. This allows for early software development, thereby enabling hardware/software co-development. It includes pre-silicon validation of software and acceleration of RTL simulation. It also enables architechtural exploration, proof of concept and customer demonstrations.

Post Silicon Validation

Using a well defined validation methodology and capabilities across pre-silicon development cycle, Open-Silicon enables hardware and software verification in post-silicon bring up phase. These include electrical checks, device characterization, function and performance qualification, and various tests based on customer requirements.

Hardware Board Design and Development

Printed Circuit Boards (PCBs) developed might be silicon validation bring-up boards, form factor evaluation boards, or system boards for production. Open-Silicon’s PCB design team has experience in areas as diverse as networking modules, medical systems, smartphones, multimedia boards, and audio conferencing systems.


Production and GDS2 Handoffs

Customers may want to take advantage of Open-Silicon’s attractive foundry mask and wafer pricing, or Open-Silicon’s ability to offshore test, or lower packaging costs.  Whatever the need, Open-Silicon’s manufacturing teams are ready to assist customers with a seamless handoff, thorough internal checklists for production release, and state-of-the-art equipment in both foundry and laboratory to make sure the ramp is successful.

World-Class Partners

Open-Silicon partners with world-class foundries to provide complete manufacturing services. Our staff brings years of semiconductor manufacturing experience and product engineering expertise to every engagement.

We work closely with the customer to identify and select the right process and technology solution for each design. Selecting the process node and the optimal process options requires careful comparison between different foundries, design objectives, market applications and target price. Our manufacturing experts pride themselves in staying current with all existing and emerging process technologies to ensure complete choice through our OpenMODEL™.

Best-In-Class Production Controls

Open-Silicon’s experienced Production Control (PC) team plays a crucial role once the customer releases their part to production. This team performs and monitors the following activities to guarantee on-time delivery:

  • Scheduling, planning and forecasting

  • Wafer, assembly and test management

  • Inventory management

  • 24×7 automated WIP tracking and reporting via ASICView

  • Shipments tracking


A Complete Solution

Open-Silicon provides a complete solution, from package selection, through design & development and into high-volume manufacturing. We understand the importance of selecting the proper packaging solution to meet the technical and cost constraints of each design. Our packaging capabilities are very broad and our experience level very deep to meet the unique needs of each customer to successfully launch their product into any of the following:

  1. Wafer-level chip scale packages

  2. Low-cost leadframe packages

  3. The full range of BGA packages

  4. High-performance flip chip packages

  5. Organic and ceramic packaging

  6. Multi-Chip Packages, including both stacked and side-by-side die configurations

  7. Signal and power integrity modeling of packages and PCBs

  8. High-performance interface design, including >10GHz SerDes, high speed DDR2/3, and WiMAX


A Complete Test Engineering Solution

Open-Silicon views test engineering as an essential part of the design process, so we address test very early in the design cycle. Our test engineers have extensive design for testability (DFT) experience with a variety of automatic test equipment (ATE). This allows us to create a smooth transition from a simulation environment to a tester environment, thus avoiding getting stuck in endless loops while debugging test vectors.

Open-Silicon’s test engineering capabilities include:

  • Ultra low-cost digital test

  • High-performance digital test including high speed interfaces

  • Analog and mixed-signal test

  • RF test

Product Engineering

Yield Enhancement

Maximum Yield


The primary goal of Open-Silicon’s Product Engineering Group is to maximize the yield of chips from each wafer produced. We monitor yields on regular basis and work closely with both the foundry engineers and the assembly house to address any process drift or changes that may cause yield issues.

As part of the debug process, we perform failure analysis upon any Return Material Request (RMA) and issue 8 Discipline (8D) reports explaining the root cause of the problem and the corrective actions that need to be taken to avoid the problem in the future. We also perform product characterization at different process splits and operating conditions in order to guarantee the quality of the product. Our team assists customers during the validation and debugging phase by providing bench measurement and FIB work if required.

Open-Silicon provides a full suite of die and package qualification including burn-in, ESD, latch up, and Highly Accelerated Stress Test (HAST). We also have the capability of performing second level reliability testing.


Failure Analysis

State-of-the-Art Capabilities


Open-Silicon utilizes the latest equipment for silicon failure analysis, including:

o   E-Beam Microscopes

o   Scanning Electron Microscopes (SEM)

o   Focused Ion Beam (FIB) including Dual Beam

o   Emission Microscopes

o   Liquid Crystal Hot Spot Detection

o   X-Ray Imaging Systems

o   Scanning Acoustic Microscopes

o   Ball Shear and PULL Testers

o   Wire Pull Testers

o   Laser Markers

o   High Power Microscope Decapping Systems

o   Plasma Etchers

o   Atomic Microscopes


IP Cores

Interlaken Core (High Speed Chip-to-Chip Interface)

Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following

Interlaken Alliance specifications:

  • Interlaken Protocol Definition, v1.2
  • Interlaken Look-Aside Protocol Definition, v1.1
  • Interlaken Retransmit Extension, v1.2
  • Interlaken Dual Calendar Extension v1.0
  • Interlaken Interop Recommendations, v1.7


Key Features

  • Fully-programmable SerDes lane mapping
  • Interlaken-LA 4-channel protocol
  • Up to 56 Gbps SerDes support
  • 1.2 Tbps high-bandwidth performance
  • Interlaken Retransmit Extension support

HMC Controllers

The Open-Silicon HMC Controller IP is architected and designed to provide the highest performance and most flexible solution for integrating the many benefits of HMC technology into next-generation systems.



  • Transaction, link and logic sub-block of the physical layer
  • Seamlessly interfaces to leading third-party SerDes IP without the need for an additional PCS layer
  • Compliant with HMC specification v1.1 or 2.0; configuration register selectable
  • Support for 10Gbps, 12.5Gbps, and 15Gbps (HMC spec. v1.1)
  • Support for 12.5Gbps, 15Gbps, 25Gbps, 28Gbps, and 30Gbps (HMC spec. v2.0)
  • Support for half-width (8 SerDes lanes) and full-width (16 SerDes lanes) operation

MCMR FEC (Forward Error Correction) IP Core

Open-Silicon’s MCMR FEC IP core is a single solution to meet the requirements of different protocols like Interlaken, Flex Ethernet, and 802.3x to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of <10-15 with an input BER of >10-6, which is required by most electrical interface standards using high speed SerDes.

Built upon a flexible and robust architecture, Open-Silicon’s MCMR FEC IP core is compatible with various SerDes supporting different widths. The MCMR FEC IP supports bandwidth up to 400G with the ability to connect 32 SerDes lanes.



  • Supports up to 56Gbps SerDes
  • Supports bandwidth up to 400G
  • Support for KP4 RS (544,514) & KR4 RS (528,514)
  • Supports Interlaken, Flex Ethernet & 802.3x protocols
  • Supports configurable alignment marker
  • PRBS test pattern generator and loopback test

PCS (Physical Coding Sublayer) IP

Open-Silicon’s PCS IP is fully compliant to the IEEE 802.3 standard supporting various MAC rates like 10G, 25G, 40G, 50G, 100G, 200G and 400G.

Built upon a flexible and robust architecture, Open-Silicon’s PCS IP core is compatible with different MII interfaces for connecting to the MAC. The PCS IP is intended to support the Ethernet and Flex Ethernet interfaces.


  • Supports multi rate 10G/25G/40G/50G/100G/200G/400G
  • Supports 64b/66b encoding/decoding
  • Supports scrambling/descrambling
  • Supports configurable alignment marker
  • Supports transcoding functions
  • Supports multi-lane distribution across virtual lanes
  • Supports various statistics counters
  • Supports test pattern generation

FlexE (Flexible Ethernet) IP

Open-Silicon’s FlexE IP is fully compliant to the OIF FlexE v1.0 standard supporting various MAC client rates like 10G, 25G, 40G, 50G, 100G, 200G and 400G.

Built upon a flexible and robust architecture, Open-Silicon’s FlexE IP core is compatible with various MACs supporting different rates. The FlexE IP supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network.


  • Supports 10G/25G/40G/50G/100G/200G/400G MAC client rates
  • User configurable client rate adaption
  • Supports bonding, sub rate, channelization and hybrid capabilities
  • Supports up to eight FlexE groups
  • Supports re-sizing of FlexE client within the FlexE group