OpenFive (Open-Silicon is now a part of SiFive Silicon BU) transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software, and IP — and then continues to partner to deliver fully tested silicon and platforms. OpenFive applies an open business model that enables the company to uniquely choose best-in-class SoC & RISC-V IP, Idea-to-Silicon methodology, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150+ companies ranging from large semiconductor and systems manufacturers to high-profile start-ups and has successfully completed 350+ designs and shipped over 150 million ASICs to date. Privately-held, OpenFive employs over 500+ people in 15+ cities around the world.


OpenFive provides flexible model to engage at any stage of the design and delivers fully tested silicon packaged parts to customers.

  • Spec Handoff to Chip
  • RTL Handoff to Chip
  • Netlist Handoff to Chip
  • GDS2 Handoff to Chip


Front End Design, Integration and Verification

Design expertise around building tiny low power SoC to large scale SoC with in-house design, integration and advanced verification automated tools and methodology.

IP Development and Integration

Our IP experts work with customers and vendors to tailor IP solutions that differentiate your product, assure IP quality and reusability, and deliver first-time working silicon

Physical Design

Our innovative design methodology combined with our deep design expertise and experience in the selection, qualification and integration of third party IP, consistently delivers reliable silicon.

Wafer Manufacturing

We work closely with our customer to identify and select the right process and technology solution for each design, comparing different foundries, design objectives, market applications and target price.

Package and Assembly

SiFive provides a complete solution, from package selection, to design and development, to high-volume manufacturing.

Test, Quality and Supply Chain Management

It is through continual improvement in our processes that we consistently achieve our goal of increasing customer satisfaction and further streamlining our processes.

IP Cores

OpenFive HBM2/2E (High Bandwidth Memory) Subsystem IP

OpenFive’s HBM IP is the industry’s first comprehensive solution for integrating high-bandwidth memory into ASICs thereby achieving the ultimate high performance and low power. By integrating the HBM protocol controller, PHY and IO into one sub-system IP product, interoperability aspects between the different system components are addressed. As an early advocate of 2.5D and 3D ASIC design technologies and by leveraging its experience from the industry’s first successful 2.5D SoC SiP demonstration in 2013, OpenFive plays a key role in enabling industry applications to leverage the HBM 3D-stacked DRAM technology.



    1. HBM Controller: JEDEC DRAM Specification compliant
    2. Supports up to 3.2 Gbps per pin data rate
    3. Configurable Independent HBM Channel support
    4. Low latency operation
    5. HBM PHY: Ultra-low latency
    6. Coarse and Fine grain IO training
    7. Low power HBM memory and PHY modes
    8. Loopback support for Testability
    9. CMOS IO with programmable drive strengths
    10. Lane Repair features


OpenFive Interlaken IP Core

OpenFive’s Interlaken IP is a scalable, high-speed chip-to-chip and die-to-die interface protocol that builds on the channelization and per-channel flow control features, while reducing the number of chip I/O pins by using high-speed SerDes technology. The Interlaken IP supports the following Interlaken Alliance specifications: – Interlaken Protocol Definition, v1.2 – Interlaken Look-Aside Protocol Definition, v1.1 – Interlaken Interop Recommendations, v1.6 – Interlaken Retransmit Extension, v1.2 – Interlaken Dual Calendar Extension v1.0 Designed and tested to be easily synthesizable into many ASIC technologies, OpenFive’s Interlaken IP Core was uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows SiFive customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.



    1. Up to 1.2Tbps high-bandwidth performance
    2. 4-channel Interlaken-Look-Aside protocol
    3. Flexible user interface options: 128, 2×128, 4×128, 8×128, 256, 2×256-bit,4×256 and 8×256
    4. Interlaken Retransmit Extension support
    5. Support for 256 logical channels, plus 8 bit channel extension for up to 64K channels
    6. Support for SerDes speeds from 3.125Gbps to PAM-based 56Gbps
    7. Configurable number of lanes from 1 to 48
    8. Simultaneous In-band and Out-of-Band flow control
    9. Programmable calendar
    10. Fully-programmable SerDes lane mapping

OpenFive MCMR FEC (Forward Error Correction) IP Core

OpenFive’s MCMR FEC IP core is a single solution to meet the requirements of different protocols like Interlaken, Flex Ethernet, and 802.3x to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of <10-15 with an input BER of >10-6, which is required by most electrical interface standards using high speed SerDes. Built upon a flexible and robust architecture, SiFive’s MCMR FEC IP core is compatible with various SerDes supporting different widths. The MCMR FEC IP supports bandwidth up to 400G with the ability to connect 32 SerDes lanes.



    1. Supports up to 56Gbps SerDes
    2. Supports bandwidth up to 400G
    3. Support for KP4 RS (544,514) & KR4 RS (528,514)
    4. Supports Interlaken, Flex Ethernet & 802.3x protocols
    5. Supports configurable alignment marker
    6. PRBS test pattern generator and loopback test

OpenFive 400/200/100G Ethernet PCS IP

OpenFive’s PCS IP is fully compliant to the IEEE 802.3 standard supporting various rates like 10G, 25G, 40G, 50G, 100G. Built upon a flexible and robust architecture, OpenFive’s PCS IP core is compatible with different interfaces for connecting to the MAC. The PCS IP is intended to support the Ethernet applications in Networking and Data Centers.



    1. Single channel PCS/PMA for 100GE, 50GE, 40GE, 25GE and 10GE Ethernet ports
    2. Configuration options to support various PCS and PMA termination for Ethernet PHYs
    3. Options to support BASE-R/Fire Code FEC, the KR FEC, the KP FEC (clauses 91/134)
    4. A flexible CGMII/XGMII port, providing seamless connection to SiFive’s 100G MAC/RS IP module
    5. MAC interface supports CGMII/XLGMII, 50GMII, 25GMII and XGMII operation modes
    6. 66b/64b block, lane lock/deskew/reorder, AM insertion/deletion, scrambling and FEC
    7. Alarms and monitoring counters (e.g. symbol errors, corrected / uncorrected codewords, etc.)
    8. Test pattern generation for NRZ’s PRBS31, PRBS9, and PAM4’s PRBS31Q, PRBS13Q

OpenFive 400/200/100G Ethernet MAC IP

OpenFive’s MAC IP is fully compliant to the IEEE 802.3 standard supporting various rates like 10G, 25G, 40G, 50G, 100G. Built upon a flexible and robust architecture, OpenFive’s MAC IP core is compatible with different interfaces for connecting to the PCS. The MAC IP is intended to support the Ethernet applications in Networking and Data Centers.



    1. Single channel MAC/RS for 100GE, 50GE, 40GE, 25GE, 10GE MAC ports
    2. Optional classic (802.3x) and priority-based flow control (802.1Qbb)
    3. MAC layer processing, including full statistics in both transmit and receive directions
    4. Supports VLAN tagged frames (IEEE 802.1Q) and double-tagged frames (QinQ).
    5. FCS checking and generation, Supports padding of small (<64 byte) frames.
    6. Interpacket gap generation based on Deficit Idle Counter
    7. Simple user (MAC service) interface, consists of a single segment of 128, 256, 512 or 1024 bits.
    8. Three separate media independent interfaces provide connection to specific PCS/PMA modules
    9. Pause frame generation is controlled through the user I/F Xon/Xoff input sideband signals.
    10. IEEE 1588v2 TSN support using an optional module

OpenFive FlexE (Flexible Ethernet) IP

OpenFive’s FlexE IP is fully compliant to the OIF FlexE v1.0 standard supporting various client rate like 10G, 25G, 40G, 50G, 100G, 200G and 400G. Built upon a flexible and robust architecture, OpenFive’s FlexE IP core is compatible with various MACs supporting different rates. The FlexE IP supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network.



    1. Supports 10G/25G/40G/50G/100G/200G/400G MAC client rates
    2. User configurable client rate adaption
    3. Supports bonding, sub rate, channelization and hybrid capabilities
    4. Supports up to eight FlexE groups
    5. Supports re-sizing of FlexE client within the FlexE group

OpenFive USB3.2 Gen2 single lane Re-Timer IP Core

OpenFive’s single lane USB3.2 Gen2 Re-Timer IP is compliant to USB3.2 Appendix E Re-Timer. It includes USB3.2 Gen2 single lane PCS layer. It is validated using FPGA prototype.



    1. Compliant to USB 3.2 Appendix E
    2. Supports all low power states
    3. Include USB3.1 Gen2 compliant PCS
    4. 8/10 Enc/Dec for Gen1 and 128/132 Enc/Dec
    5. SRIS (Separate Reference clock Independent SSC) based Architecture
    6. Support for both Local and Pass Through loopback
    7. Control and Status registers accessible through APB bus
    8. Optional support for PHY with PIPE interface

OpenFive USB3.0 DR-OTG Controller IP Cores

OpenFive’s USB3.0 DR-OTG Controller IP is compliant to USB3.0 OTG specification and certified as Device Controller and Embedded Host Controller. It supports both Gen2 and Gen1 and AXI4 for system integration. It is validated using FPGA prototype with industry standard PHYs.



    1. Compliant to USB 3.0 Rev1.1 and OTG & EH supplement Rev1.0
    2. Backward compatible USB2.0 with (optional) 3rd party USB2.0 OTG controller
    3. Support to 8/16/32 bit standard PIPE interface
    4. Compliant to 32-bit AXI system bus interface
    5. Supports Default Control Endpoint 0 and Endpoints up to 15 IN & 15 OUT
    6. Configurable burst sizes for each Function Endpoint
    7. Supports Bulk Streaming and smart isochronous feature
    8. Support for all spec defined Low Power States
    9. Fully Integrated DMA controller (optional)
    10. Option to disable scrambling, Monitor Link States, Endpoints and FIFOs

OpenFive USB3.2 Gen2 IP Core

OpenFive’s USB3.2 Gen2 Device Controller IP is compliant to USB3.1 Rev1.0 and certified at USB-IF. It supports both Gen2 and Gen1 and AXI4 for system integration. It is backward compatible to USB3.0 and USB2.0 with 3rd party USB2 Controllers. It is validated using FPGA prototype with industry standard PHYs.



    1. Support to 32-bit standard PIPE interface
    2. Compliant to AXI-4, Support 32/64/128-bit bus
    3. Supports Function Endpoints up to 15 IN & 15 OUT
    4. Configurable burst sizes for each Function Endpoint
    5. Supports Bulk Streaming feature and Smart Isochronous feature
    6. Option to switch to USB3.1 Gen1 only mode
    7. Support for all Low Power States and Clock gating options for power saving
    8. Fully Integrated SG DMA (Optional) with configurable number of channels up to 32
    9. Option to disable scrambling, Error, Event and Link States monitoring

OpenFive Die-to-Die Controller IP

OpenFive’s Die-to-Die (D2D) Controller IP is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple die either on Interposer or on Organic Substrate. Die-to-Die Controller IP offers unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration.




  • Ultra-high-bandwidth and performance (For e.g. 1024-bit AXI interface at 2GHz can provide up to 2 Tbps)
  • Ultra-low latency including Tx and Rx depending on the optional FEC module to improve BER
  • Support for the SerDes rates up to 112 Gbps (CEI-112G-XSR) and aggregation support up to 48 lanes
  • Independent SerDes lane enable/disable and fully programmable SerDes lane mapping
  • Flexible AXI interface options including 64b, 128b, 256b, 512b and 1024b
  • Optional In-band and Out-of-Band flow control
  • Built-in error detection and interrupt structure
  • Optional re-transmission module for error-free transmission
  • Configurable error injection mechanisms for testability
  • Debug Features: PRBS generators/checkers and loopback support for both data and flow control