Rachip

Israel

Rachip is One Stop R&D Center, provides software & hardware development services.

 

Rachip teams have been involved in more than 100 tape-outs in recent years, and have the capability to deliver a chip, from architecture and design to full manufacturing.

 

Rachip employs 150 R&D experts with vast experience in ASIC/FPGA Design and Verification, Backend, ESL SystemC and Validation services, Firmware and Embedded SW, QA and Automation as well as Web/Mobile apps, for a wide range of projects across the telecoms, network processing, data storage, military, aviation, medical, and automotive sectors.

 

Rachip works closely with multinational companies as well as startups. We provide our varied customers highly skilled local teams, with flexibility on project scope & budget.

Services

System Architecture Definition

  • Definition of the ASIC Architecture to meet the customer’s system requirements
  • System Level and SoC microarchitecture development
  • HW and SW partitioning to generate a balanced solution
  • System level SoC verification in the early stages of the definition using ESL SystemC modelling.

IP & SoC Verification

  • System level SoC verification in the early stages of the definition using ESL SystemC modelling.Verification
  • Module/top level SoC verification
  • Verification with advanced methodologies (Specman/SystemVerilog/SystemC)
  • e-based/SystemVerilog random and constraint driven verification
  • Verification Expertise in UVM – Universal Verification Methodology
  • Formal verification
  • Functional coverage analysis
  • Mixed signal verification
  • Gate Level verification including SDF

Design

  • High Level Design
  • Micro Architecture Documentation
  • RTL Coding with VHDL or Verilog
  • Low power awareness technics

Synthesis and Backend

  • Floor planning
  • Synthesis and DFT insertion
  • P&R and timing closure
  • Cadence and Synopsys tools
  • Low power optimization
  • P&R and timing closure
  • Timing and SI-aware place and route
  • Full-chip RC ¬†extraction
  • Full-chip timing/SI closure, static timing analysis and sign-off
  • Full-chip physical verification (DRC)
  • Full chip Logic Vs Schematic verification (LVS)
  • Chip finishing and Tape-Out
  • Automatic Test Pattern Generation (ATPG)
  • Cadence and Synopsys tools

SoC Post Silicon Validation

  • Firmware development team
  • Board design services
  • Performance analysis and validation