Ready Group – (formerly Rachip)

Israel

The Ready Group has been a leading R&D service firm in Israel since 2007. Our wide range of technical expertise enables the next generation of technology and products of leading multinational and Israeli companies as well as innovative startups in various stages.

 

Our chip and software development proficiencies are applied to many technology sectors such as Semiconductors, Telecom, Automotive, Fintech, Agritech, Military and Aviation, Business Applications, Medical, Government, IoT, Big Data and Machine Learning, Autonomous Systems, and more.

 

With over 200 professionals in various technical domains. We provide chip development services from architecture and design to full manufacturing.

Services

System Architecture Definition

  • Definition of the ASIC Architecture to meet the customer’s system requirements
  • System Level and SoC microarchitecture development
  • HW and SW partitioning to generate a balanced solution
  • System level SoC verification in the early stages of the definition using ESL SystemC modelling.

IP & SoC Verification

  • System level SoC verification in the early stages of the definition using ESL SystemC modelling.Verification
  • Module/top level SoC verification
  • Verification with advanced methodologies (Specman/SystemVerilog/SystemC)
  • e-based/SystemVerilog random and constraint driven verification
  • Verification Expertise in UVM – Universal Verification Methodology
  • Formal verification
  • Functional coverage analysis
  • Mixed signal verification
  • Gate Level verification including SDF

Design

  • High Level Design
  • Micro Architecture Documentation
  • RTL Coding with VHDL or Verilog
  • Low power awareness technics

Synthesis and Backend

  • Floor planning
  • Synthesis and DFT insertion
  • P&R and timing closure
  • Cadence and Synopsys tools
  • Low power optimization
  • P&R and timing closure
  • Timing and SI-aware place and route
  • Full-chip RC ¬†extraction
  • Full-chip timing/SI closure, static timing analysis and sign-off
  • Full-chip physical verification (DRC)
  • Full chip Logic Vs Schematic verification (LVS)
  • Chip finishing and Tape-Out
  • Automatic Test Pattern Generation (ATPG)
  • Cadence and Synopsys tools

SoC Post Silicon Validation

  • Firmware development team
  • Board design services
  • Performance analysis and validation