Sidense’s 1T-Fuse(TM) Logic NVM IP is based on a patented, one-time programmable (OTP) technology that provides the most cost-effective and reliable OTP solution in the industry. No additional mask layers or process steps are required and the IP is portable across many different technology nodes, process variants and foundries. The OTP can be programmed in the field, at wafer probe, or during production testing. Sidense memory products are targeted to standard-logic digital CMOS processes that are 180nm to 20nm and below and are available for all Top-Tier foundries and selected IDMs.


Additional features include field-programmability, a emulated multi-time programmable (eMTP) mode, a very small footprint using one transistor per bit, programming voltages supplied on-chip, very fast read-access times, greater than 10-year retention at 125°C and a 100% read cycle, and conversion to mask ROM with a single diffusion mask and no process changes.

IP Cores


Sidense SHF One-Time-Programmable (OTP) memory IP is based on a patented 1T-Fuse™ (anti-fuse) bit-cell. The 1T-Fuse bit-cell uses gate oxide breakdown as a robust, non-reversible programming mechanism. Optimized for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.


Sidense SHF memory IP is provided as a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded SoC applications. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self-Test (BIST) RTL. SHF applications include: code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.




SiPROM provides the broadest range of process node coverage – from 130nm down to 55nm. Densities up to 512 Kbits per macro are available and multiple macros can be used for higher memory capacity, making SiPROM an ideal and field-programmable replacement for masked ROM and, in certain applications, external Flash memory. Designers can choose between four read modes to trade off memory density, read access time, enhanced reliability and enhanced security, and different read modes may be combined in the same macro.


SiPROM macros contain a built-in charge pump, which provides the voltage necessary to program the memory in the field after the chip is packaged. Alternately, programming voltage may be supplied externally through a pad on the chip.


Other SiPROM features include Row Redundancy as a row repair mechanism, a Boot Row Register for additional parallel outputs, Security Locks to disable programming of all or part of the macrocell, and a Mask ROM Option needing only a single mask change to mask program all or part of the memory,


SiPROM uses include HDCP encryption keys, analog trim and calibration, boot code and firmware storage, Chip ID, RFID, and other mobile and wireless, medical, and automotive applications.



SLP macros are currently available at 180nm, at densities up to 256 Kbits per macro. These macros were designed for very low power applications, such as handheld wireless, remote sensor and implanted medical devices.


SLP macrocells include several additional features that provide flexibility in customizing the memory operation to target specific applications.


Read Mode Options:  By default, the OTP macrocells are read in single-ended mode utilizing one memory cell per logical bit of information. Two additional read modes are provided for enhanced margins and an extra level of data security needed for highly reliable, field-programmable systems: differential mode and redundant mode.


Special Operating and Test Modes:  The SLP macrocell has special operating and test modes, such as sense amplifier test mode, word-line test mode and bit-line test mode that can be enabled in order to reliably test the macrocell. Unlike most OTP, testing can be achieved on both the programmed and the un-programmed cells.


Mask ROM Option:  SLP macros can be converted into mask-programmable ROMs with a single mask change. The user has the flexibility to mask program the entire memory or individual portions of the macrocell.


Optional Power Supply Macro:  SLP macros can be combined with an optional power supply macro to allow the customer to program the SLP macrocell in the field after the chip is packaged.


SLP applications include handheld and wireless devices, implanted medical devices, configurable storage, and RFID tags. They are ideal replacements for masked ROM or flash memory in many applications.



ULP macros are designed to minimize active and standby power consumption, with standby power less than 0.25µA. The macros are currently available at 180nm, in several configurations ranging from 16 bits to 2 Kbits, and multiple macros can be combined to meet larger memory requirements ULP macros are designed to be low-power, field-programmable replacements for eFuses in applications such as precision analog trimming in automotive, medical, wireless and other systems.


Programming of the ULP macro may be done with an external voltage source or with an optional power supply macro that supplies the programming and read voltages from a single VCC supply. The required read voltage is a very low 1.5V and programming current requirements are much smaller than those needed for programming eFuses. The default read mode of the macro – differential/redundant – provides the highest level of chip security and reliability. ULP data is available at chip start-up.


ULP macros can be converted into mask-programmable ROMs with a single mask change. The user has the flexibility to mask program the entire memory or individual portions of the macrocell. This feature gives the customer the ability to mask program a section of the memory while allowing other sections of the memory to be programmed in the field.