Signature IP
USA
After several years of incubation, Signature IP was founded in 2021 to develop advanced Network-on-Chip (NoC) solutions that form the basis for a full platform for SoC design. Signature IP features 120+ person-years of engineering leadership in interconnect, networking, datacenter, storage and connectivity IP, from specification to production. Our team has an extensive engineering background with expertise in interconnects, interfaces, bus protocols, CPUs and AI processing.
At Signature IP, “we strive to speed SoC design” by making the design of the NoC – the backbone of the chip – fast, flexible and configurable. By enabling our customers to easily change the NoC topology, experiment with different configuration settings, and instantly simulate the results to measure throughput and latency, we make it possible to explore the design space at the top level of the chip before making major architectural decisions. When customers are ready to prototype or implement the NoC, our pushbutton RTL generation connects directly with customers’ EDA and FPGA environments. Our SaaS tool architecture makes tool access easy and reduces the burden on their IT department.
IP Cores
NC-NoC
NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC supports multiple clocking schemes and multiple protocols such as AXI4/3, AHB, APB, AXI-lite and multiple bus widths from 32 to 2048 bits. It provides power control through power-islanding and a power-gating architecture at the interface port and router level.
NC-NoC is physically aware, providing automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and generation of power and frequency-aware NoC generation.
NC-NoC delivers high performance though any-to-any connections at multiple levels. Its packetized architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.
C-NoC
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It has configurable data bus widths, supports multiple clocking schemes, and is physically-aware with auto-pipelining and grouping of routers to meet timing requirements. C-NoC supports multiple protocols including CHI, AXI4/3 and AXI-lite, ACE and ACE-lite.
C-NoC provides power control through power-islanding and a power-gating architecture at the interface port and router level, and is physically aware with automated insertion and deletion of pipelines to meet timing, generation of placement-aware groups and topologies, and power and frequency aware NoC generation.
C-NoC provides high performance with on-chip L3 cache support to reduce memory access latency, and its pipeline architecture provides scalability with maximum throughput and minimum latency. It is parity enabled to provide resiliency.
PCIe Gen6 Controller
Our latest PCIe gen 6 controller IP, which is “NoC aware”, provides a high-speed interface for efficient data transfer and system communication, supporting speeds of up to 64 GT/s. We are currently in the final stages of development and encourage interested customers to contact us for early access to take advantage of its advanced features and capabilities. Stay ahead of the competition and contact us today to learn more.
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