Terminus Circuits


Terminus Circuits offers High Speed Serial Link Interface IPs and provide interconnect solutions across many standards like USB.org, PCIe-SIG, IEEE, SATA, VESA etc. These transceivers are an integral part of any HPC systems providing interconnect solutions that scale bandwidth and deliver end-to-end signal integrity in next-generation platforms. These robust PHY IPs are available for different foundries and broad spectrum of process technologies. Terminus Circuits delivers low power, small form factor, low latency, integrated clocking and biasing, interconnect IPs that are pervasive in virtually all of today’s semiconductors.





SerDes based PHY design/CAD proven and test chip development.

IP Cores

SerDes Interface

Terminus Circuits SerDes architecture is in production in processes ranging from 65nm to 28nm for Global Foundries and TSMC. The PHYs comes complete with a Physical Media Attachment (PMA) that supports multi-protocols and physical Coding Sublayer (PCS) that is PIPE4.3 compliant. The SerDes comes with Bandgap circuits with ±3% variation for biasing the PLL, TX, RX and other circuits. For receiver-end the system is equipped for Clock and Data Recovery (CDR) circuit which can extract both clock and data from incoming data stream. CDRs are offered up to 3000PPM for SerDes based applications.


  • Supports PHYs including PCI Express Gen4/3/2/1, USB 3.1 Gen2/1, SATA Gen 3/2/1, 10GBase-KX4, 1000Base-KX, 10GBase-KR / XFI, XAUI, DisplayPort, HSSTP, EPON/GPON/XGPON, SGMII/QSGMII etc.
  • Data rates of 1Gb/s to 16Gb/s
  • Modular Rx and Tx
  • Scalable architecture for multi lane implementation
  • Low latency


Analog PLL

Terminus Circuits provides low Jitter analog PLLs with very high Q-inductor based LC Oscillator. We offer PLLs at 8 GHz, 10 GHz and 16GHz. They are suitable for high speed interface and RF clocking needs.


  • Fast settling – sub micro second
  • Quadrature outputs
  • Process nodes – 28nm to 65nm
  • Fabs – TSMC, Global Foundries


Digital PLL

Terminus Circuits provides low Jitter and small form factor digital PLLs based on Ring Oscillators. We offer PLLs at 1.25 GHz, 2.5 GHz, 4 GHz, and 5 GHz. They are suitable for clocking high speed interface and multi-Standard wireless communication systems.


  • Quadrature outputs
  • Capacitor tuneable range of +/-20% for the process variations
  • Process nodes – 28nm to 55nm
  • Fabs – TSMC, Global Foundries