752 Views

Accurate Performance Analysis Requires Package Modeling

January 24, 2018, anysilicon

System performance is a critical requirement for the vast majority of integrated circuits that are designed today. To meet these stringent performance requirements, IC designers invest considerable time and effort in accurately modeling and simulating chip level performance – all to avoid nasty surprises when the first chips return from fabrication. Performance modeling and simulation covers a broad range of analyses and tools, including high-level cycle based analysis of top level system blocks and interconnect, power analysis based on interconnect and switching data, static timing analysis to identify critical timing paths, and detailed circuit and electromagnetic (EM) simulations to characterize critical subsystems.

 

One aspect of performance modeling that is often neglected is package parasitics. Ignoring or only approximating package parasitics can significantly reduce the accuracy of a model, resulting in simulations that fail to accurately identify performance issues prior to tapeout. It could, for example, (1) cause the predicted matching in an RF circuit to be off, (2) cause improper characterization of the expected ground bounce in fast switching, high current circuits, or (3) fail to accurately predict resistive losses in high current circuits. Any of these could result in significant amounts of debug work in the lab. Worse yet, they could lead to an unexpected degradation in performance that is exposed only after the chip is fabricated.

 

RF circuits aren’t the only circuits susceptible to degradation from the effects of packaging. A large percentage of ASICs and SoCs with fast switching circuits (e.g. DC-DC converters) will be affected, and will benefit from models that include package parasitics.

 

Modeling Package Parasitics

Properly modeling and simulating package parasitics is key to accuracy, and to first pass success. Intrinsix has substantial accumulated experience modeling various die package types, including wire bond, flip chip, and flip on lead packages. From this, we’ve learned that there are several points to keep in mind when constructing and simulating package models.

 

Collaboration Is Key

It’s absolutely essential to collaborate with the packaging vendor to construct a model with the required detail. The vendor will be able to provide comprehensive package specifications including diagrams, physical dimensions, and electrical characteristics. The information needed for a package model will depend on the type of package. For flip chips, accurate values for ball height and diameter are required; for bond wires – length and diameter. In addition to information about the package, die thickness of the chip will need to be incorporated into the model as well. Accurate values for these will directly impact the fidelity of the model, and its ability to accurately predict performance related characteristics of the chip.

 

3-D-image-of-IC-with-lead-frame-and-band-wires.png

Illustration 1: 3-D image of IC with lead frame and bond wires

 

Capable Electromagnetic Modeling and Simulation Environment

Once the packaging information, pin out, and preliminary pad ring have been established, the package model can be constructed.[1] This should be done in the context of a capable electromagnetic (EM) simulator[2] that is able to perform S-Parameter simulations, and can accurately analyze the 3-D EM effects associated with high-speed RF IC packages and bond wires.

 

Simulation and Modeling Strategies

When performing the EM simulation, there are trade-offs between the range of frequencies that are analyzed versus the time required to perform the simulations. This trade-off should be carefully considered. Failure to analyze a large enough frequency range could result in a missed resonant frequency caused by the package.

 

Simulation bottlenecks can be avoided by realizing that it’s not always necessary to perform EM simulations on the full package. It’s often sufficient to include just a small subset of critical I/O.  Typically this includes the highest frequency and highest current I/O. Since supply and ground pins will carry the highest current loads, they are usually included in the analysis. Keeping the package model to its essential minimum will allow the simulations to run faster, with fewer convergence issues.

 

To illustrate the importance of accurate package modeling, consider the S11 plots shown in the diagram below. Each plot illustrates the quality of IC input impedance matching over a range of frequencies, where the best matching is represented by the lowest S-Param values. As can be seen in the diagram, a significant frequency shift can be seen in the narrow band match when simulating with and without the package model. Failure to adequately characterize the matching RF band prior to tapeout can cause expensive debug and rework.

 

S11 with and without a model of the IC package

Illustration 2: S11 with and without a model of the IC package

 

Clearly the package can have a large impact on IC performance. At Intrinsix, package modeling and simulation are an integral part of the design flow. In our experience, the effort to develop a detailed and accurate package model is well worth the investment. It will form a solid, accurate basis for exploring and characterizing the performance related behavior of your chip prior to tapeout – reducing the risk of expensive surprises

 

[1]          Slight changes to the pad ring later in the project may not always impact the model, but care should be taken to evaluate these changes, and update the model if necessary.

[2]          Keysight’s ADS is an example of a capable EM simulator that Intrinsix has experience with

 

____________________________________

This is a guest post by Chris Bulla of Intrinsix