Find companies providing DDR IP cores

IP Cores

SoC White Box IP, Wireless Connectivity, Wired Connectivity, Broadcast IP, Video & Graphics

Services

Intellectual Property (IP) & Process Technology, SoC/ASIC Development Platform, Design Flow, Packaging & Testing, Production Service, Application-Oriented Value-Added Services

IP Cores

USB3.1 Gen1 IP Solutions, Technology Optimized Standard Cell Library, ESD Robust Multi-Voltage I/O, Low Power SRAM with High Production Yield

Services

Circuit Design, Product Development, Memory products, IP and consulting, Test Consulting

Services

Custom Analog Mixed-Signal ASIC Solutions, ASIC, SoC, FPGA Design Services, Design Verification, Silicon Validation, IC Design Services, DFT Services

IP Cores

Microcontrollers and IDE solution, Custom Memory IP and I/Os, DDR3/DDR2 Memory Controller, 3D Graphics Processor for Wearables/IoT, Gigabit Ethernet PHY Cores, Wired and Wireless Connectivity

Services

RTL Design, FPGA to ASIC conversion, Place and Route with Timing verification, Package Design, Wafer Fabrication, COT Services

IP Cores

High-speed ADC/DAC, Multi-rate SerDes, BroadR-Reach Compliant Ethernet PHY, AFE, DisplayPort, HDMI, DisplayPort & HDMI, Processor

Services

ASIC Design Services, FPGA Design Services

IP Cores

RISC-V CPU Core, DDR4 Controller + PHY

Services

Basic Vendor Selection Package, Full Silicon Management Package, Verification Package, Silicon Roadmap Planning Package, Commercial Package, Financing Package

Services

IP Core development, IP Core customization, System-on-Chip

IP Cores

CPUs and MCUs, Peripherals, Debugging Tools

Services

ASIC services, IP Design

Services

ASIC Design and Verification, Physical Implementation, VIP Development, Embedded Systems

Services

ASIC Design Services & Implementation, ASIC turnkey Operation , Crypto Coin & Block Chain ASIC , Supply Chain Management , RF & Mixed Signal, IP Design and Licensing

IP Cores

1.6GHz Phase-Locked-Loop (PLL) , 6.5Gbps Multiprotocol SERDES PHY (GF 65nm), 12.5Gbps Multiprotocol SERDES PHY (GF 40nm), 1.6GHz Phase-Locked-Loop (PLL) (GF 65nm), Multi-Protocol Physical Coding Sublayer (PCS)

Services

ASIC & FPGA Design & Development, Physical Design and DFT, Hardware Design, Verification & Validation

IP Cores

Reference Designs & EVMs

IP Cores

Ring Based PLL’s, LC PLL’s, SerDes Interfaces, LVDS Interfaces, Oscillators

Services

Digital Design Verification (DV), Digital Microarchitecture, Design, & Implementation, Analog Modeling & Mixed Signal (AMS) Verification

IP Cores

Security & Encryption, Standard Interconnect and Communication Protocols

Services

Physical Design, RTL Synthesis and verification, STA

IP Cores

DDR