Find companies providing IOs and Library IP Cores.
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Turnkey ASIC Design, IP Blocks Design, Radioelectronic Devices Development
RF Transceivers, PLL, ADC, Process, Voltage and Temperature Sensors (PVT sensor/detector/controller), RFID (UHF tag, ID card, NFC, medical implants), Energy harvesting (power converters from RF-field to voltage and current)
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SoC Design, Supply Chain Management, ASIC Services, FPGA Design
Processor IP, Digital and Analog IP
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Digital Verification, Physical Design, DFT – Design for Testability, Analog, Mixed Signal, RF & Power Management, Tech Foundation IPs (Standard Cell, Memory & IO), Embedded Systems
Hardware Accelerator for Crypto currencies, Interface IPs: SERDES, DDR, GPIO, LVDS, PLLs– Phase Lock Loop, Data Converters: ADCs and DACs, Power Management IPs
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ASIC Services, Mixed Signal Services, Spec-in / Turnkey Services
High Speed Serdes solutions, High end, high speed ADC/DAC, Low-Power, Cost-Effective 8- and 16-bit MCUs, Video, Image & Data Compression, MIPI, RF
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Intellectual Property (IP) & Process Technology, SoC/ASIC Development Platform, Design Flow, Packaging & Testing, Production Service, Application-Oriented Value-Added Services
USB3.1 Gen1 IP Solutions, Technology Optimized Standard Cell Library, ESD Robust Multi-Voltage I/O, Low Power SRAM with High Production Yield
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IP Provider, IO Design, Consulting and testing services
Low Voltage ESD/EOS protection (up to 5V), HV/BCD EOS/ESD protection (5V and higher), LIN PHY (transceiver) , Programmable Clipping Circuit for Antenna pins, Power-on-Reset Circuit, Radiation Hard, ESD robust Level Shifters
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IC Design Services, IP Development, RFID, Design Tools, Technologies, System Design
Radio Frequency Identification (RFID), Power Management, Medical Microelectronics, Data Conversion
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Design Services, Foundry Access, Custom IP, Turnkey Solution, makeChip Hosted Design Service Platform
0.4V Standard Cell Library for 22FDX (22nm FDSOI), Adaptive Body Bias Solution for 22FDX (22nm FDSOI)
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IP Integration
Microcontrollers and Processors, Video and Image Compression, Data Compression, Interconnects and Interfaces , Peripherals, Controllers, and Security, AMBA System Infrastructure and Functions
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Design Services
Standard Cells Libraries, TCAM & CAM, SRAM & ROM, Custom PDK and PCELL, Register Files
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Basic Vendor Selection Package, Full Silicon Management Package, Verification Package, Silicon Roadmap Planning Package, Commercial Package, Financing Package
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Fabless Semicoductor Supplier, Design Services – Analog & Digital ASIC design, Design Services – FPGAs, Design Services – IC Lifecycle Management – EOL Redesign
Analog IP Cores, Digital IP Cores
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SiPass Silicon Platform as a Service, System in Package (SiP) Turnkey Service, ChipStarter Multi-Client ASIC Programs
Analog and Mixed Signal IP, Graphic and Peripheral IP, Interface Controller & PHY IP, Memory and Logic Library IP, Multimedia & Wireless Communication IP, Processor & Microcontroller IP
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Custom Analog Mixed-Signal ASIC Solutions, ASIC, SoC, FPGA Design Services, Design Verification, Silicon Validation, IC Design Services, DFT Services
Microcontrollers and IDE solution, Custom Memory IP and I/Os, DDR3/DDR2 Memory Controller, 3D Graphics Processor for Wearables/IoT, Gigabit Ethernet PHY Cores, Wired and Wireless Connectivity
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General-Purpose I/O (GPIO), ESD Protection , High-speed I/O, Memory Interfaces, Special
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ASIC design, ASIC verification, Silicon validation, Turnkey (full supply chain services)
Microcontrollers and IDE solution, Embedded Memory and Standard Cell Libraries, High resolution audio converters / High resolution measurement converters
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ASIC Design Services & Implementation, ASIC turnkey Operation , Crypto Coin & Block Chain ASIC , Supply Chain Management , RF & Mixed Signal, IP Design and Licensing
1.6GHz Phase-Locked-Loop (PLL) , 6.5Gbps Multiprotocol SERDES PHY (GF 65nm), 12.5Gbps Multiprotocol SERDES PHY (GF 40nm), 1.6GHz Phase-Locked-Loop (PLL) (GF 65nm), Multi-Protocol Physical Coding Sublayer (PCS)
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