March 12, 2015, anysilicon
The corner-based timing signoff approach is a historical and traditional method that has justified a development and enhancements of conventional STA tools and signoff flows. The number of signoff corners exponentially grows along with an increase of variation sources, their magnitude, and timing margins. It becomes a bottleneck in the design flow and leads to an over-margining, over-design, a loss in the System-On-Chip (SoC) performance, timing yield, costs, etc. It causes a timing signoff deadlock and still does not guarantee against a silicon failure. This paper exam-ines the situation and outlines possible solutions.
The corner-based timing signoff methodology and the corner number used in this methodology increase the duration of the timing signoff, make timing closure difficult and worsen most of design metrics. The corner-based timing signoff is a justification for the current design flow and contemporary signoff tools. It has multiple impacts on the design flow, Time-to-Market (TTM), cost, SoC performance F, timing yield Y, etc. It becomes a problem for getting the most benefits from moving to next advanced technology nodes. You can find all the details in white paper . The same paper also discusses the conventional timing signoff methodology in details. It pro-vides a definition of the current timing closure and the timing yield. It shows that the conven-tional timing signoff does not support the timing yield as a design signoff requirement and it be-comes a challenge. Then, timing derating (margins) methods of contemporary STA tools, which should cover for variations, are considered. An increase of variation sources and their magnitude leads to losses in the SoC performance and diminishes other design metrics. Some limitations of current derating methods are considered and, then, it is shown that Statistical STA (SSTA) tools provide a partial solution but are not panacea. Later, in this paper , we consider a signoff optimism and conservatism (pessimism), different variability sources and, finally, the timing si-gnoff deadlock.
Chapter 2 provides important design recommendations on selecting and minimizing timing signoff corners.
Chapter 3 provides design and timing signoff recommendations and tips that will minimize delay variations and, in most cases, are the same for the corner-based methodology and new statistical methodologies. They include discussions on corners and minimization of their number, using the useful skew, and variations in paths with zero and a useful skew.
Chapter 3 provides important design recommendations and timing signoff tips on how to minimize delay variations in cells by reducing slew and load.
This is a guest post by Dr. Alexander Tetelbaum, CEO of Abelite Design Automation