December 05, 2013, anysilicon
This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.
Lock-Up Latches are important elements for STA engineer while closing timing on their DFT Modes: particularly the hold timing closure of the Shift Mode. While shifting, the scan chains come into picture, which are nothing but the chains of flip-flops involving the output pin of one flop, connected to the Scan-Input or Test-Input pin of the other flip-flop, and so on, forming a chain.
Now, imagine that we have two functionally asynchronous domains 1 and 2. By functionally asynchronous, we mean that during the normal mode of operation (i.e., the functional mode), the two domains do not interact with each other. However, very rarely do designers have the liberty to make a separate scan chain for functionally asynchronous domains. Let’s consider the following scenario where domain 1 has the average clock latency of 3ns, and domain 2 has the average latency of 6ns. And the time period of the test clock is, let’s say 10ns.
Now, let’s see the timing checks for this scenario. The output of the last flip-flop of the domain 1 is part of the scan-chain and is connected to the Test-Enable input of the first flop of domain 2. The timing check would be like:
Owing to the positive clock skew, the setup check would be relaxed, but the hold check would be critical. There are two possible options to fix the hold timing:
The first might not be a robust solution because the delay of the buffers would vary across the PVT corners and RC corners. In the worst case, there might be a significant variation in the delays across corners and you might witness closure of timing in one corner, but violation in other corner!
The second solution is a more robust solution because it obviates the above scenario. Let’s see how it does it. As evident by the below figure, we have inserted a negative level triggered latch (called as lock-up latch) between the two flip-flops which had a significant difference in their clock latency.
Now the timing check would be like:
As evident from the above figure, both setup and hold checks are now relaxed.
To read more blogs from Naman, visit http://vlsi-soc.blogspot.in/
Image credit: ckaiserca