Low-Power VLSI Design Methodology

October 28, 2014, anysilicon

Low Power Design is the today’s need in VLSI. Why? Well, ask yourself ! You go to gadget shop, looking for a new cell-phone. Apart from the price, what are the qualitative things that you would be most concerned about?


  • Features including the speed of the processor
  • Battery back-up
  • Operating System

A good Operating system can make an efficient use of the system’s hardware resources but is more driven by the software applications that you wish to run. However, the first two are directly influenced by the design methodology and the technology node that goes behind designing your device.


You would love to buy a cell-phone with a faster processor to enable you to have your applications run fast, your computations quicker. Also, you wouldn’t want to charge your cell-phone every hour. Or for that matter everyday! This would translate into a design challenge to have your device to consume least power.

Frequency and power go hand-in-hand. You cannot just go on increasing the frequency (assuming that timing is met!), without expecting any hit on power.


Power, itself has many components. To just give you a glimpse, we’ll talk about the components of power in brief.

Power dissipated has two components: Dynamic and Static.





Dynamic power constitute that component of total power which comes into picture when the devices (the individual transistors) switch their values from either 0 to 1 or vice-versa. Dynamic power itself has two components:

  • Capacitive Load Power: Depends on the output load of each transistor switching states.
  • Short Circuit Power: Depends on the input transition.




Static Power is the component which is dissipated when the device is not switching i.e. it is in standby mode and mainly constitutes of leakage power.


We talked about the fact that Power and speed of the device go hand-in-hand. It is pretty much evident from the above equation. As you tend to increase the frequency of your design (again emphasizing that timing must be met!), the switching rate of the devices would increase and hence capacitive load component of the dynamic power would increase.



One turn-around to reduce power is to reduce the voltage supply at which your devices are working. But this, in turn, will reduce the signal swing available for the devices to cross the threshold voltage ( Vt ) and hence would engender myriad design challenges.


Before I conclude this post, I would like to make one last point. The device complexity is increasing every day and the device size is shrinking. This ensures that your latest cell-phone is sleek in its look but again, hit is on Power!





The above table shows the trend of ever-increasing power dissipation with scaling down of technology nodes. This has forced the designers to come up with innovative design solutions to deliver the best to you.

In upcoming posts, we will discuss these design-for-low-power solutions in detail.


[1] Low Power Methodology Manual: For System on Chip Design by Michael Keating, David Flynn, Robert Aitken, Alan Glibbons and Kaijian Shi.



This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India. To read more blog posts from Naman, visit http://vlsi-soc.blogspot.in/