June 23, 2015, anysilicon
ASIC is otherwise known as application-specific integrated circuits. These specific circuits can be designed to customer specification and customized for one particular use. There are chip designs for almost any type of application and in many cases these products are designed as the building blocks for high-efficiency processes on one major application.
An example of ASIC design could include a chip that’s capable of running a Bit coin miner at high-efficiency or an electronic digital voice recorder. These circuits can be designed to fit into various forms of hardware and even mass-produced.
ASIC designs are definitely miniaturized over the past few years as well as increased in complexity. ASIC designs standardized at around 5000 logic gates a few years ago and today many are designed with over 100 million logic gates. Many modern ASIC’s also included memory blocks, microprocessors, analog functionality and more. These types of modern ASIC designs are often referred to as System on Chip (SoC) designs because they have all of the building blocks of electronic hardware included.
When determining the functionality of any application-specific integrated circuits, many designers use a special hardware description language called Verilog or in some cases VHDL. This language will go on to describe everything that an ASIC can accomplish.
The most basic ASIC designs available on the market include:
Standard cell: This type employees at mask of a custom-designed and silicon semiconductors made up from stock components. This type of circuit does have some flexibility available and can meet manufacturer requirements without the need for a full custom design.
Gate array: This is a stock ASIC design with bulk silicon layers in a standard configuration. If a manufacturer requires a vast amount of standard functions to occur in a particular manner to meet simple requirements, a gate array ASIC can often inexpensively fill a need.
Full Custom ASIC: these types of designs offer full flexibility. The entire layout is matched to the requirements of the circuit with a design that goes right down to the transistor level. These costs can be considerably more in the development time is much longer than the other two. Results can be a little more unpredictable but ultimately the entire design can end up working more efficiently and in a much more miniaturized format than with standard cell or gate array.