Key takeaway: Compare the total cost per qualified good die, not merely the quoted wafer price. Start by determining whether you are adding an already-qualified manufacturing site, porting to a different foundry process at the same nominal node, or migrating to a different technology node.

Why do semiconductor companies change wafer foundries?

Fabless semiconductor companies and integrated device manufacturers (IDMs) evaluate alternate wafer fabs for several interconnected reasons.

• Wafer pricing and long-term economics. A second source may offer a more competitive manufacturing price, different minimum order commitments or better commercial terms. The opportunity must survive yield, testing, logistics and non-recurring engineering (NRE) costs.
• Geographic and geopolitical diversification. Manufacturing across different countries or regions can reduce dependence on a single exposure to export restrictions, trade policy, natural disasters or regional disruption. Physical locations matter—not just the foundry company’s headquarters.
• Capacity and lead-time risk. An alternative source can support production ramps, buffer allocation constraints or extend the life of a mature-node product.
• Business continuity and process longevity. Companies may respond to an end-of-life notice, scheduled fab closure, process obsolescence or reduced support for particular process options.
• Technical improvement. An alternative process might offer better yield, power-performance-area (PPA), analog performance, voltage capability or manufacturing quality.
• Customer requirements. Automotive, industrial, aerospace and regulated customers may request an approved second source or more resilient supply chain.

First determine what kind of transfer is actually possible

The term wafer fab transfer is often used for three different technical situations.

Considering an alternative wafer foundry?

AnySilicon can help you structure the initial evaluation and identify potential foundry and engineering partners based on process technology, capacity, geography and product requirements.

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How process node affects the complexity: 180nm to 3nm

Generally, advanced logic nodes have substantially higher mask, design, verification and IP costs. Yet node size alone is a poor predictor of migration difficulty: a highly customized 180nm BCD or CMOS image sensor process can be harder to replicate than a relatively standard digital implementation at a smaller node.

The ranges are qualitative engineering judgments, not universal ratings. The “3nm” label does not itself imply a common transistor architecture or drop-in compatibility across suppliers. Technology options and IP availability are more decisive than a shared node name.

Why analog and BCD transfers are often underestimated

A mixed-signal or high-voltage ASIC may depend on particular lateral DMOS devices, drift regions, thick-oxide transistors, precision resistors, capacitors, trim circuitry, latch-up margins and layout-dependent effects. A receiving fab may advertise the same 180nm node but lack a required 60V device, embedded NVM module or proven reliability characteristic. The circuit must then be redesigned, re-characterized or split across technologies. These risks should be identified before requesting a production wafer quotation.

Why advanced-node transfers are rarely mask-only exercises

At 28nm and below, reusable RTL may preserve functional intent, but physical implementation is tightly coupled to the foundry’s process design kit (PDK), standard-cell libraries, SRAM macros, hard IP, extraction models and signoff rules. At 7nm, 5nm and 3nm, implementation and verification effort, mask expense and third-party IP licensing can dominate the program. Review technology access and export-control restrictions before assuming an alternate source is available.

What does it cost to change wafer foundries?

The correct budget separates one-time transfer investment from the recurring cost per saleable chip. A quote that lists only mask price and wafer price is incomplete.

Illustrative early-stage budget allowances (USD): For a low-change, already-matched manufacturing-site introduction, a planning allowance might be $100,000–$500,000; for an independent mature-node port, roughly $300,000–$2 million or more; for a complex 65nm–28nm design, $1 million–$10 million+. At 16nm–3nm, full porting programs can run to many millions or tens of millions of dollars, and large complex SoCs may cost much more. These are rough scenario-planning ranges proposed for initial discussion, not measured market averages, published foundry tariffs or supplier quotations. Program scope can fall outside them, particularly where custom IP, advanced packaging or several silicon spins are involved. A qualified-site introduction may also be funded by the manufacturer rather than directly charged to a fabless customer.

Published discussions of ASIC manufacturing economics and mask-set expenses show why a transfer budget depends heavily on technology and implementation scope. See AnySilicon’s mask-cost guide and semiconductor manufacturing cost breakdown.

The cost-per-good-die test

Simplified cost per good die = wafer fabrication price ÷ (gross dies per wafer × effective wafer-sort yield)

Then add packaging, final test, logistics, scrap, warranty risk and other recurring items as applicable. When comparing foundries, account for differences in wafer diameter, die area, edge exclusion, test coverage and yield.

Illustrative example: The cheaper wafer that is not cheaper per chip.
Current fab: $1,800 per wafer, 1,000 gross dies, 90% effective wafer-sort yield = $2.00 per good die.
Alternative fab: $1,600 per wafer, 1,000 gross dies, 80% effective wafer-sort yield = $2.00 per good die.
The 11% lower wafer price produces zero wafer-level cost-per-good-die savings in this example, before any transfer NRE or qualification expense. All figures are hypothetical.

How to calculate foundry transfer payback

Annual net savings = annual good-chip demand × (current fully loaded cost per good chip − new fully loaded cost per good chip) − additional annual dual-source overhead

Suppose a company spends $480,000 transferring an industrial ASIC and expects $240,000 in annual net savings after accounting for yield and test. The simple payback is two years. Management should also consider the product’s remaining lifetime, inventory exposure, forecast uncertainty and the value of avoiding a supply interruption.

How long does a wafer foundry transfer take?

Timing depends on the availability of a qualified receiving process, design documentation, PDK and IP access, prototype slots, customer approvals and the number of silicon iterations. The following stages may overlap.

1. Feasibility & RFQ
2. PDK & IP gap analysis
3. Design & signoff
4. Prototype & test
5. Qualification & approval
6. Ramp & transition

Illustrative sequence: design and customer readiness tasks may run in parallel, but production release follows required validation and approvals.

Durations are illustrative planning assumptions, not fab lead-time guarantees. Automotive or safety-critical approvals, a failed qualification, missing IP or a silicon respin can extend schedules substantially.

Indicative end-to-end planning windows

Important exception: an automotive 180nm BCD product can take longer than a less regulated digital project on a smaller node. Milestones should be based on the actual product and qualification plan rather than node size alone.

What testing and qualification are required?

A change of foundry can affect electrical distribution, defects, reliability, traceability and supply quality. The evidence required depends on what changed and who must approve it. Product and process requalification are not interchangeable.

1. Baseline the existing production device. Record wafer-sort and final-test limits, yield, critical parameters, reliability data, process control data and customer specifications.
2. Demonstrate process capability. Review receiving-fab qualification, process control monitors (PCM), statistical process control (SPC), critical equipment/process differences and wafer maps.
3. Verify new silicon against the original. Compare PVT (process, voltage, temperature), analog accuracy, leakage, timing, power, high-voltage behavior, ESD/latch-up, and functional corners. Conduct A/B correlation where possible.
4. Qualify reliability to the applicable requirements. Plan HTOL, temperature cycling, humidity bias/HAST, ESD, latch-up, electromigration, TDDB or other stresses according to the product and potential failure mechanisms—not by copying a generic checklist.
5. Confirm assembly and test compatibility. Validate wafer thickness, pad locations, passivation, bumping or wire bond, test guardbands, probe cards and traceability.
6. Complete change notifications and approvals. Applicable requirements may include JEDEC J-STD-046 product-change notifications, JESD47 stress-test qualification, AEC-Q100 for automotive ICs and customer-specific contractual processes. Assess whether the product, manufacturer or downstream customer owns each approval.

Qualification is risk-based. As Infineon’s supplier PCN guidance explains, moving fabrication, assembly or test to an unqualified site is a relevant change-notification category. In some cases where the same process and techniques have already been qualified at the receiving site, the required evidence can be narrower than a full new-technology qualification; this must be justified and accepted for the specific product. 

Wafer foundry transfer checklist: questions to resolve before commitment

Use this as a go/no-go checklist during a formal request for quotation (RFQ) or foundry comparison.

Technology and design

• Is the receiving technology truly compatible with required operating voltage, device types, reliability and process options?
• Are PDKs, verified models, DRC/LVS decks and extraction/EDA flows available and mature?
• Can standard cells, SRAM, NVM, IO, ESD, PLL, SERDES and other IP legally and technically move?
• Who owns the design database, reticles, hard IP and modified layout, and are existing agreements restrictive?
• Are changes required to die area, pad ring, bump map, package or thermal design?

Operations and supply

• Is sufficient qualified capacity available at the exact fab site, process option and wafer diameter?
• What are the cycle-time, prototype schedule, full-mask lead time and minimum volume?
• Can the supplier show yield data, process capability, quality systems and PCN/traceability practices?
• Are export controls, country-of-origin requirements, tariffs and disaster-recovery dependencies acceptable?
• Are packaging, test, bumping, substrates and logistics truly diversified—or do both wafer sources share a downstream bottleneck?

Economics and product release

• Have all NRE, prototype spins, mask sets, IP licenses, qualification, test tooling and transition inventory been budgeted?
• Does the comparison use fully loaded cost per good chip rather than wafer price?
• Who funds a failed silicon spin, engineering change, yield shortfall or delayed qualification?
• What evidence and customer approvals are required before production shipment?
• What is the old-source exit plan, last-time buy policy and dual-source inventory strategy?

Common practices: how experienced teams reduce transfer risk

• Do not immediately abandon the incumbent fab. If possible, maintain supply while the second source is qualified. An orderly overlap protects customer deliveries and allows old/new product correlation.
• Start with a feasibility gate. Ask a receiving foundry or qualified design house to review non-sensitive process requirements before releasing sensitive GDSII, source code or proprietary IP.
• Preserve the package and test interface where practical. Keeping the device pin-compatible and minimizing changes to test hardware can lower risk; however, do not force equivalence at the expense of reliability.
• Use MPW or a reduced-risk engineering lot when appropriate. A shuttle can validate the most critical analog blocks, memories or PDK assumptions before committing to production masks. MPW availability varies by process.
• Set objective signoff gates. Define upfront acceptable shifts in yield, critical electrical parameters, reliability, timing, power and cost-per-good-die.
• Contract for the migration—not just wafer supply. Confirm engineering ownership, deliverables, qualification data, capacity, customer notifications, corrective actions and commercialization responsibilities.
• Check for hidden single points of failure. An alternative foundry does not provide geographic independence if both manufacturing paths rely on one OSAT, substrate provider, test house or constrained material.

When staying at the current foundry may be better

A transfer may be difficult to justify when the product has limited remaining lifetime, annual wafer volume is low, third-party IP cannot be licensed at the target process, qualification risk is unacceptable or the apparent wafer saving disappears after yield loss and NRE amortization. Alternatives include negotiating a longer-term supply agreement, securing capacity allocation, redesigning only the next product generation, or maintaining safety stock while a second source is developed.

How to request a meaningful quotation from an alternative wafer foundry

Provide a concise, comparable RFQ package: current and target node; device function; wafer diameter; digital/analog/BCD/RF options; critical voltages and temperature range; mask and die size; high-level IP dependencies; expected annual wafer starts; package/test requirements; target geography; qualification needs; desired production date; and whether the goal is price reduction, second sourcing or complete replacement. Request a separate quote for feasibility, design porting, masks, prototypes, qualification and volume manufacturing.

Ask each candidate to clearly state assumptions, exclusions, engineering support, PDK maturity, committed capacity and who owns the qualification work. A quoted process node and price per wafer are not sufficient grounds for selecting a new source.

Frequently asked questions about changing wafer foundries

Can I transfer my existing masks to another foundry?

Usually not. Masks are fabricated for a particular manufacturing process and set of design rules. A genuinely replicated, qualified process may offer an exception, but most transfers between independent foundries require new masks and at least some process-specific redesign.

Is moving from one 180nm foundry to another easy?

Not necessarily. Analog, BCD, high-voltage, RF and embedded-memory options can differ substantially. Two technologies advertised as “180nm” are not guaranteed to support the same devices or layouts.

What is the difference between a foundry transfer and a node migration?

A foundry transfer changes the manufacturing source. A node migration changes the manufacturing technology generation or platform. A project may involve one or both. The latter often introduces much greater design and IP changes.

Does adding a second wafer foundry mean I have a true second source?

Only when the alternate product is approved, deliverable in the required volume and equivalent under the customer’s specifications. Also examine packaging, testing, materials and transport dependencies.

How much qualification is needed for an automotive IC?

The scope depends on whether the change is a new process, a fab-site addition or another manufacturing change, plus the applicable AEC-Q100, JEDEC and customer-specific requirements. The customer quality team should agree on the qualification and PCN approach before the change is released.

What is the biggest mistake in a foundry migration?

Comparing wafer prices before confirming process compatibility and full good-die economics. A cheaper process that requires major analog redesign, new IP or extensive qualification may have a worse total cost and longer time to production.