Sofics

Belgium

Sofics is a semiconductor IP provider based in Belgium. We provide specialty I/Os and ESD protection to more than 100+ customers worldwide. Fabless companies using Sofics IP can enable higher performancehigher robustness and reduce design time and cost. Our technology has been characterized on leading foundries like TSMCSMICUMCGFSamsung FoundryHHGrace and more.

 

Our customers have integrated Sofics IP into more than 5000 IC designs across many different application verticals. Sofics IP is used in 40% of recent Bluetooth products, billions of smartphone imager chips, over a billion FPGA chips, most of the indoor positioning applications, in several car models and keys, optical communication modules for datacenters from multiple vendors and many other applications….

Services

IP Provider for unique I/O and ESD protection

Sofics’ fabless customers use foundry provided IO pads for the general purpose interfaces. For more difficult requirements they rely on Sofics IP:

 

  • Higher ESD robustness requirement for e.g. DisplayPort/HDMI/USB/… or automotive interfaces (more)
  • Lower parasitic capacitance for high-speed interfaces (30% to 50% lower capacitance) (more)
  • Lower leakage for wireless or sensor interfaces (100x lower compared to foundry) (more)
  • Flexibility for e.g. cases where IO-segments are used instead of an IO-ring
  • Fail-safe, hot-swap, cold-spare interface requirements (more)
  • Higher voltage tolerance (e.g. 5V tolerant pad) (more)
  • Reduced total ESD area (more)

Custom I/O and ESD Design

Sofics offers robust circuit and interface solutions, including custom digital I/O’s, circuits that handle transient disturbances (e.g. to provide antenna clipping or POR), as well as automotive standard PHYs (e.g. a full LIN PHY with integrated ESD, EOS and EMC robustness).

 

We developed several analog circuits to e.g. enable I/O circuits with higher voltage tolerance. We have supported several such projects where we provide a custom I/O circuit, e.g. with fail-safe option

 

Examples

  • 1.8V I/O based on 1.2V transistors in Samsung 4nm FinFET (link)
  • 3.3V I/O based on 1.8V transistors in TSMC 28nm CMOS (link)

IP Cores

Low Voltage ESD/EOS protection (up to 5V)

Sofics offers a wide range of ESD/EOS/latch-up solutions, silicon proven in a variety of CMOS/SOI/FinFET processes. Porting to another process is always possible. Process coverage.

The solutions are optimized for cost, robustness and performance:

  • Cost: save on silicon cost (small area), time to market, and mask sets
  • Robustness: any standard (HBM, MM, CDM, IEC 61000-4-2, IEC 61000-4-5, JEDEC78, …), any level
  • Performance: low capacitance, low leakage, overvoltage tolerant, …

 

More info about all the features on the Sofics website

HV/BCD EOS/ESD protection (5V and higher)

Sofics offers ESD/EOS/Latch up/EMC solutions for HV and BCD processes. The solutions are tailored for demanding applications, such as automotive, industrial or medical.

Specifications include

  • On-chip ESD HBM/MM/CDM
  • System level ESD on-chip (IEC 61000-4-2, ISO 10605)
  • Automotive disturbances (ISO 7637-2 & -3)
  • EMC specifications (IEC 62312, ISO 11452)

 

More info about ESD solutions for BCD in the article

LIN PHY (transceiver)

Automotive interfaces can be challenging to design, due to a large set of reliability specifications, such as EMC or automotive disturbances such as described in ISO 7637.  Sofics has developed a LIN transceiver (PHY) for 12V batteries, conforming to the LIN specification document (ISO 179870), including driver, ESD protection, EMC protection etc. (LIN controller not included). The PHY can be ported to different BCD processes. More info in the article

Programmable Clipping Circuit for Antenna pins

A clipping circuit to limit the voltage of input signals coming from an antenna pin. The clipping voltage can be selected (currently 2 options) or disabled. The circuit is product proven for NFC applications in TSMC 65nm, but can be ported to any desired process. More info in the article.

Radiation hard circuits

Need IP for radiation hard applications? Sofics has IP blocks product proven proven for aerospace applications. More info in the article.

IP for chiplet Die-2-Die interfaces

For chiplets’ die-2-die interfaces the ESD robustness can be reduced a lot. There is opportunity to reduce area, capacitive loading, leakage.

 

Some background and details about specs and summary presentation.

 

Sofics has been involved in Co-packaged Silicon photonics projects for 10+ companies. We have supported chiplet projects with ultra-small, low-cap ESD protection for the die-2-die interfaces. Sofics engineers have supported several stacked image sensor projects.