The minimum amount of time before the active clock edge before which the input signal must become stable so that the data may be correctly captured at the next clock edge is referred to as the setup time.
Setup time is a characteristic of flip-flops and it is modeled in the timing libraries as a function of input slew at the data pin and the slew at clock pin. Setup time violations impose a limit on the maximum achievable clock frequency of the system. Setup checks are typically done at the worst PVT conditions, taking into account the worst case delays and worst case slews. Positive clock skew, lowering clock frequency and faster data-paths facilitate setup timing closure.
