ams OSRAM offers industry-leading expertise in ASIC design. Our global network of analog, digital, verification, and process engineers, spread across 40+ research and development centers, is equipped to tackle any demanding ASIC project. We combine comprehensive design capabilities in analog, mixed-signal, and digital techniques, followed by rigorous verification throughout the design phase.
– Our CMOS processes enable semiconductor devices, like photodiodes and low-noise transistors, to be customized to meet sophisticated customer needs.
– We ensure precise modeling to accurately reflect simulation in reality.
– If desired, we provide chips as bare dies on foil or packaged in ceramic housing within a week after fab-out day.
– Once packaged, your products are assessed for full functionality and specification compliance.
Owning our CMOS fabrication plant gives us a unique advantage, enabling close collaboration between design and process engineers to fine-tune semiconductor devices. This ensures the perfect process option tailored to your specific application. Our Process Design Kit (PDK) offers resources for developing complex analog and mixed-signal designs, including accurate simulation models, libraries, IP blocks, and verification rule sets. Our dedicated teams in Austria provide precise models and comprehensive technical support.
Our “first-time-right” approach ensures high-quality results, with designs undergoing rigorous verification at multiple stages, supported by top-of-the-line CAD software. Active customer participation in design reviews ensures the final product meets all requirements. We maintain consistent versioning of models and tooling to ensure smooth unification and verification of the block in the pre-tapeout phase.
Every design undergoes extensive validation in our state-of-the-art laboratories, equipped with certified and calibrated equipment. This high level of automation enables efficient data tracking and minimized development time. Where time is constrained, we can deliver the first samples in ceramic packages within a week of wafer manufacturing.