Germany
Creonic is the ISO 9001:2015 certified leader in ready-for-use IP cores, offering a rich services and product portfolio for wired, wireless, fiber, and free-space optical communications. Covering essential digital signal processing algorithms such as forward error correction, modulation, equalization, and demodulation, as a preeminent provider, our solutions support industry standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, and Wi-Fi.
Designed for ASIC and FPGA technologies, Creonic’s products meet the highest benchmarks of quality and performance. Trusted by dozens of customers worldwide, from innovative start-ups to global corporations, our IP cores power communications devices and chipsets, satellites, and NewSpace ventures, enabling unparalleled reliability and success in advanced communication systems.
We offer customized solutions for individual needs:
Optimization of the IP cores for the selected ASIC technology node, with a focus on minimizing power consumption and VLSI area to precisely meet customer specifications. A holistic approach and comprehensive optimization methodology are employed to achieve these objectives.
Optimize your development process with our advanced IP core integration services for your platform. Creonic specializes in seamlessly integrating our IP cores into the FPGA fabric, connecting them with third-party IP cores like JESD204 or DMA cores. Additionally, we provide a comprehensive software API that enables you to easily control and monitor the status of our IP cores.
By choosing our integration services, you can save valuable time and resources while significantly reducing development time.
The development of complex communications systems should not only rely on the acquisition of IP cores. According to our experience, a look at the whole system shows high potential for more powerful and yet more efficient implementations.
Therefore, Creonic offers you communications system design services for ASIC and FPGA. Our know-how comprises the integration of many components of signal processing. We are able to adapt these components to your system to your specific requirements and match the components accordingly. In the end you can show your customer an extraordinary system.
Do you want to implement a communications system on the microelectronic level? Do you need support for the migration of your algorithms from the software to hardware level? Benefit from the experience of our team. We are happy to advise you with respect to microelectronic implementation in the fields of communications and FPGA integration in general.
Communications
We can provide you with advice on the implementation of algorithms for digital signal processing in the fields of wired and/or wireless communications. It doesn’t matter whether you are designing a standard-based (e.g., LTE, DVB) or proprietary system.
FPGA-Integration
Do you want to set up a demo system based on FPGAs? Do you want to port an algorithm onto FPGAs to drastically reduce simulation times? Or do you just want to extend your knowledge in the field of FPGA implementation?
IEEE 802.3bj Reed-Solomon Encoder and Decoder
The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
IEEE 802.11n/ac/ax (Wi-Fi 6) LDPC Decoder and Encoder.
The Creonic IEEE 802.11 LDPC decoder is a high-performance implementation for WLAN and further applications and supports all LDPC codes as defined by the standard.
FEC Encoder and Decoder including constellation shaping for optical high-speed application.
SDA OCT V3.0 Encoder and Decoder
The Creonic SDA OCT V3.0 Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC).
ITU 25GPON
The Creonic ITU 25G PON LDPC Encoder and Decoder support the default LDPC (17280, 14592) coding scheme, as well as the optional LDPC (17152, 14592) scheme. The IP cores are available for ASIC and FPGAs (AMD Xilinx, Altera/Intel, Microchip).
Creonic provides IP cores for wideband (500 Msymb/s) DVB-S2X demodulation, LDPC/BCH decoding as well as Modulation.
The Creonic DVB-S2X wideband modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4 Gbit/s for 256-APSK). The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 Msymb/s on state- of-the-art FPGAs. The Creonic DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on state-of-the-art FPGAs.
The Creonic AWGN Channel IP core is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP core was developed with the aim of allowing the performance evaluation of a digital communication system in the presence of Additive White Gaussian Noise.
5G-NR
Creonic’s 5G LDPC Decoder and Encoder IP cores provide a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.
4G LTE
Creonic’s LTE/LTE-A IP Core is an advanced, customer proven implementation of the standardized 3GPP turbo code. The turbo decoder was designed forbase station and user equipment applications. However, the high flexibility in block lengths and code rates makes it the ideal fir for further applications.
