Allegro DVT

France

Allegro DVT offers H.264, HEVC, VP9, AV1, VVC, LCEVC Encoder, Decoder, Pixel Processing Semiconductor IPs. Allegro DVT proposes these multiformat Encoder and Decoder IPs ensuring selectable video codecs, scalability through a multicore architecture and ultra-low latency all on a minimum silicon area. Its Semiconductor Video IPs portfolio also include an AI-Based Neural Video Processor and a range of flexible Pixel Processing IPs. 

 

Allegro DVT continues to offer high-end Compliance Streams through its Video Compliance Tools product line, bringing togaether all the essential tools for video analysis in a single portfolio.
Discover Allegro DVT’s Video Compliance Tools product line featuring Sirius Elementary Streams, Streamwise System Streams, and dedicated Lab Testing Services product families.

Services

Sirius Elementary Streams

Allegro DVT’s Sirius Elementary Streams are Video Test Streams to ensure decoder compliance with video codec standards.

  • Avoids expensive re-design phases and shortens development cycles. Due to their high complexity, video decoders need to be extensively validated ahead of production.
  • Strengthens the decoder against all possible encodings, existing ones or future streams, to extend final products’ life.
  • Future-proof your products to prepare mass production. Increase target product

long-term operability by ensuring it will comply with today and tomorrow’s broadcast.

  • Each streams suite targets a specific profile/level combination.

 

Elementary Streams include following CODECS:

Streamwise System Streams

Allegro DVT’s Streamwise System Streams are System-Level Test Streams to ensure receiver compliance with broadcast standards.

Verify system compliance and robustness before mass deployment to end users. Thanks to Allegro DVT system test streams, IC vendors, OEMs and broadcasters can be confident that their products will comply with today’s and tomorrow’s broadcasts.

 

Allegro DVT system streams are specifically designed to ease system testing. They provide two levels of verification: quick visual check or in-depth and accurate analysis with measuring tools.

 

Streamwise System Streams include:

IP Cores

Juno Neural Video Processor IP

Allegro DVT’s NVP300, AI-based Neural Video Processing IP, pushes video quality to the next level by leveraging the advanced features and benefits of AI-based video processing technologies.

The NVP300 IP features an optimized hardware implementation to deliver real-time AI processing of 4K video within best-in-class silicon area and power budget suitable for embedded products. It implements a range of AI-based algorithms to enhance the subjective quality of video and reduce noise to achieve better compression ratios.

• AI-based Video Processor IP to enhance video quality
• Wide range of picture resolution from HD up 8K via multicore
implementation
• Optional video pre/post processing
• Selectable bit depth and chroma subsampling formats
• Optional embedded MCU for easier software integration
• Highly optimized PPA suitable for ASIC integration

 

Features:

  • Programmable Bit depths (8, 10, 12-bit)
  • Programmable Chroma Subsampling Formats (4:2:0, 4:2:2, 4:4:4)
  • Optional Built-in MCU
  • Supported Resolutions from HD30 up to 8K120

 

Wide range of optional Pre-Post Processing Features:
– Color Space Conversion
– Crop and Resize filters
– Bit depth and Chroma Subsampling format conversion

Prism Video Encoder IP

High Throughput Multi-Format Video Encoder IP

  • Selectable video codecs
  • Selectable bit depth and chroma subsampling formats
  • Scalability through multi-core architecture
  • Optimized silicon area
  • Low power consumption

E100 Series

 

Allegro DVT’s E100 Series of Encoder IP enables HD/1080P60 resolution encoding up to 5MPixels in a single core.

The E100 Series Encoder is built around a true multi format architecture that shares resources between the H.264, H.265, VP9, AV1, JPEG compression standards, while providing superior video encoding quality.
The E100 Series Encoder IP also has multiple new smart encoding features allowing customers to considerably reduce the bitrate to meet their application specific requirements.

 

E300 Series

 

Allegro DVT’s E300 Series of Encoder IP features a new hardware architecture that minimizes the silicon area while enabling 4K resolution encoding in a single core and beyond in a multi-core configuration.
The E300 Series Encoder is built around a true multi format architecture that shares resources between the H.264, H.265, VP9, AV1, JPEG, VVC compression standards, while providing superior video encoding quality.
The E300 Series Encoder IP also has multiple new smart encoding features allowing customers to considerably reduce the bitrate to meet their application specific requirements.

 

E301

 

E301 is Allegro DVT’s MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) encoder IP solution.
The E301 LCEVC encoder IP is optimized for power and silicon area, making it suitable for system-on-chip (SoC) designers to easily integrate LCEVC decoding. It supports up to 8Kp60/120 resolution as well as up to 12-bit pixels and 4:4:4 chroma format.

Pulsar Video Decoder IP

High Throughput Multi-Format Video Decoder IP

  • Selectable video codecs
  • Selectable bitdepth and chroma subsampling formats
  • Scalability through multi-core architecture
  • Optimized silicon area
  • Low power consumption

 

D100 Series

 

D100 Series is the Allegro DVT’s ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking to integrate a high-performance video decoding solution into their chips.
Built upon a true multi- format architecture, the D100 Series Decoder IP core provides a highly flexible solution up to HD/5Mpixels resolution and selectable video codecs.
D100 Series supports H.264, HEVC, VP9, AV1 and JPEG formats. The D100 Series Decoder IP core also generalizes the ultra-low latency decoding down to sub-frame latency and features 8-, 10-bit support and chroma sampling of 4:2:0, 4:4:4.

 

D300 Series

 

D300 Series is the Allegro DVT’s ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking to integrate

high-performance video decoding solutions into their chips. Built upon a true multi-format architecture, the D300 Series Decoder IP core provides highly scalable solution up to 8K resolution through their multi-core architecture and selectable

video codecs.

 

The D300 Series Decoder IP core also generalizes the ultra-low latency decoding down to sub-frame latency for all mainstream video formats: H.265, H.264 and JPEG. With 8-, 10- and 12-bit support and supporting chroma sampling of 4:2:0, 4:2:2 and 4:4:4, this decoder core is truly market leading.

 

D301

D301 is the Allegro DVT’s MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) decoder IP solution. The D301 LCEVC decoder IP is optimized for power and silicon area, making it suitable for system-on-chip (SoC) designers to easily integrate LCEVC decoding.

It supports up to 8Kp60/120 resolution as well as up to 12 bit pixels and 4:4:4 chroma format. LCEVC is an innovative video standard that enhances all existing video codecs including H264, HEVC, VVC and AV1 without the need to replace them. LCEVC delivers better video quality up tu 40% lower bitrate and enables HDR video coding.

Zinia Pixel Processor

A range of flexible pixel processing IPs to build an optimized and high-performance video processing pipeline.

• Wide range of conversion functionality including scaling, cropping, rotating, mirroring, color space, chroma format, bit depth conversion, OSD

  • Wide range of picture resolution from HD up to 8K via multicore implementation
  • Optional embedded MCU for easier software integration
  • Highly optimized PPA suitable for ASIC integration

 

Allegro DVT’s PP300 IP is a flexible Pixel Processor that provides a wide range of processing functions.

 

The PP300 IP offers various system integration options by providing either memory or direct pixel interfaces for input/output pixels.

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