ASIC vs FPGA Break-Even: When the Economics Flip

The question most teams ask is simple:

“At what volume does ASIC become cheaper than FPGA?”

The problem is that the question is usually asked too late, and answered too simplistically. There is no single magic number where ASIC suddenly becomes the obvious choice. The real break-even point depends on how you think about cost, risk, and product lifetime.

This article explains how experienced teams think about the ASIC vs FPGA break-even point in practice, why simplistic comparisons are misleading, and how to reason about economics before committing to a direction.

Why the naïve comparison fails

A common comparison looks like this:

• FPGA unit cost vs ASIC unit cost
• Multiply by volume
• Subtract NRE

If the math turns positive, ASIC “wins.”

This model is appealing because it is simple. It is also incomplete.

FPGA cost is not just the silicon price. ASIC cost is not just the die. Both have hidden multipliers that change the economics over time.

Teams that rely on a naïve spreadsheet often delay the ASIC decision until they have already paid a significant opportunity cost.

What FPGA really costs over time

FPGA cost shows up in more places than procurement spreadsheets.

Beyond the unit price of the device, FPGA-based products typically carry:

• Higher power consumption, which affects batteries, thermals, and enclosures
• Larger boards and more components, increasing assembly cost and yield risk
• Performance headroom limits that constrain feature growth
• Margin pressure that scales linearly with volume

These costs repeat with every unit shipped. They compound quietly as volume grows.

Early on, this is acceptable. At scale, it becomes strategic.

What ASIC really costs upfront

ASIC shifts cost forward in time.

Instead of paying a tax on every unit, you pay a large portion of the cost upfront in the form of NRE: engineering effort, verification, IP, tapeout, and manufacturing setup.

The economic question is not “Is NRE high?”

It is “Can NRE be amortized across enough units, shipped for long enough, to justify the shift?”

This is why volume and product lifetime matter more than almost any other variable.

The break-even curve, not the break-even point

In reality, break-even is not a point, it is a curve.

On one axis, you have cumulative shipped volume.

On the other, total cost of ownership.

FPGA starts low and increases steadily.

ASIC starts high and increases slowly.

The intersection of those curves depends on:

• Expected annual volume
• Product lifetime
• Unit cost delta between FPGA and ASIC
• Power, packaging, and manufacturing differences
• Cost of redesigns or supply disruptions

Two products with the same annual volume can have very different break-even outcomes depending on these factors.

Typical volume ranges (directional, not promises)

While every project is different, experienced teams often see patterns:

• Below ~10k units per year: FPGA usually wins on flexibility and speed
• 10k–50k units per year: economics are ambiguous and context-dependent
• 50k–200k units per year: ASIC often starts to make economic sense
• 200k+ units per year: ASIC economics are usually compelling if the spec is stable

These are not rules. They are starting points for discussion.

Ignoring lifetime, power, and integration can easily move these ranges up or down.

The hidden accelerators of break-even

Certain factors pull the break-even point earlier than teams expect:

• Severe power constraints that force expensive system-level workarounds
• Integration pressure that reduces board cost and assembly risk
• Long-term supply or availability requirements
• Performance limits that block revenue-generating features

When these factors are present, the “economic” argument for ASIC often becomes stronger even at moderate volumes.

Why teams miss the moment

Many teams stay on FPGA too long not because ASIC is wrong, but because the decision feels irreversible.

In reality, the most expensive mistake is waiting until the economics are obvious to everyone. By then, margins are already under pressure, and competitors may have moved earlier.

The goal is not to jump into ASIC prematurely. The goal is to recognize when the economics are shifting and plan accordingly.

How to think about break-even correctly

A practical approach is to stop asking “What is the break-even volume?” and start asking:

• What is our realistic volume range over the product lifetime?
• How much unit-cost relief would ASIC provide?
• What recurring costs does FPGA impose beyond silicon price?
• How stable is our specification today?
• What happens if we delay the decision by one year?

These questions usually clarify the direction faster than any spreadsheet.

What to do next

If you are unsure whether your product is approaching the break-even zone, the right next step is not a detailed cost model. It is a directional decision check that tells you whether ASIC makes sense now, later, or not at all.

Next step

Run the 2-minute ASIC or Not? Decision Wizard to see where your project sits on the ASIC vs FPGA curve and what to focus on next.

👉 /asic-or-not